llvm-project/llvm/test/MachineVerifier
Amara Emerson 55533203d7 [GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.
Differential Revision: https://reviews.llvm.org/D99383
2021-03-25 17:23:30 -07:00
..
generic-vreg-undef-use.mir
live-ins-01.mir
live-ins-02.mir
live-ins-03.mir
test_copy.mir
test_copy_mismatch_types.mir
test_g_add.mir
test_g_addrspacecast.mir
test_g_assert_sext.mir [GlobalISel] Add G_ASSERT_SEXT 2021-02-17 13:10:34 -08:00
test_g_assert_sext_register_bank_class.mir [GlobalISel] Add G_ASSERT_SEXT 2021-02-17 13:10:34 -08:00
test_g_assert_zext.mir [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT 2021-02-12 21:33:27 +00:00
test_g_assert_zext_register_bank_class.mir [GlobalISel] Add G_ASSERT_ZEXT 2021-01-28 13:58:37 -08:00
test_g_bitcast.mir
test_g_brindirect_is_indirect_branch.mir
test_g_brjt.mir
test_g_brjt_is_indirect_branch.mir
test_g_build_vector.mir
test_g_build_vector_trunc.mir
test_g_bzero.mir [AArch64][GlobalISel] Emit bzero on Darwin 2021-03-25 17:14:25 -07:00
test_g_concat_vectors.mir GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources 2021-03-01 09:10:36 -05:00
test_g_constant.mir
test_g_dyn_stackalloc.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_icmp.mir
test_g_insert.mir
test_g_intrinsic.mir
test_g_intrinsic_w_side_effects.mir
test_g_inttoptr.mir
test_g_jump_table.mir
test_g_load.mir
test_g_memcpy.mir
test_g_memset.mir
test_g_merge_values.mir
test_g_phi.mir
test_g_ptr_add.mir
test_g_ptrmask.mir
test_g_ptrtoint.mir
test_g_rotr_rotl.mir [GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates. 2021-03-25 17:23:30 -07:00
test_g_select.mir
test_g_sext_inreg.mir [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT 2021-02-12 21:33:27 +00:00
test_g_sextload.mir
test_g_shuffle_vector.mir
test_g_store.mir
test_g_trunc.mir
test_g_ubfx_sbfx.mir Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir 2021-03-24 11:23:08 -07:00
test_g_zextload.mir
test_phis_precede_nonphis.mir
test_vector_reductions.mir [GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions. 2020-10-15 15:51:44 -07:00
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir
verifier-phi-fail0.mir
verifier-phi.mir
verifier-pseudo-terminators.mir
verifier-statepoint.mir [Verifier] Add tied-ness verification to statepoint intsruction 2021-01-13 14:40:44 +07:00
verify-regbankselected.mir
verify-regops.mir
verify-selected.mir