llvm-project/mlir
Thomas Raoux 6d5aeb0dce [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write
Improve the logic deciding if it is safe to hoist vector transfer read/write
out of the loop. Change the logic to prevent hoisting operations if there are
any unknown access to the memref in the loop no matter where the operation is.
For other transfer read/write in the loop check if we can prove that they
access disjoint memory and ignore them in this case.

Differential Revision: https://reviews.llvm.org/D83538
2020-07-10 14:55:04 -07:00
..
cmake/modules Install the MLIRTableGen static library. 2020-06-11 18:23:24 -07:00
docs Add Python bindings guide. 2020-07-09 20:49:39 -07:00
examples [MLIR] Add variadic isa<> for Type, Value, and Attribute 2020-06-29 15:04:48 -07:00
include [mlir][Vector] Add folding for vector.transfer ops 2020-07-10 16:49:12 -04:00
integration_test [mlir] [VectorOps] Allow AXPY to be expressed as special case of OUTERPRODUCT 2020-07-10 12:23:24 -07:00
lib [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write 2020-07-10 14:55:04 -07:00
test [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write 2020-07-10 14:55:04 -07:00
tools Create the MLIR Reduce framework 2020-07-07 23:42:53 +00:00
unittests [mlir][spirv] Introduce OwningSPIRVModuleRef for ownership 2020-07-07 08:29:27 -04:00
utils [mlir][NFC] Remove usernames and google bug numbers from TODO comments. 2020-07-07 01:40:52 -07:00
.clang-format
.clang-tidy Fix MLIR clang-tidy: when tweaking it does not inherit from the parent 2020-03-07 17:44:21 +00:00
CMakeLists.txt Initial boiler-plate for python bindings. 2020-07-09 12:03:58 -07:00
LICENSE.TXT Add the Apache2 with LLVM exceptions license to MLIR 2019-12-24 00:58:06 -08:00
README.md mlir README.md: Fix the syntax 2019-12-24 13:31:07 +01:00

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.