forked from OSchip/llvm-project
335 lines
11 KiB
LLVM
335 lines
11 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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;
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; Note: Print verbose stackmaps using -debug-only=stackmaps.
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; We are not getting the correct stack alignment when cross compiling for arm64.
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; So specify a datalayout here.
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; CHECK-LABEL: constantargs:
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; CHECK: {{^}}.L[[constantargs_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: osrinline:
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; CHECK: {{^}}.L[[osrinline_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: osrcold:
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; CHECK: {{^}}.L[[osrcold_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: propertyRead:
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; CHECK: {{^}}.L[[propertyRead_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: propertyWrite:
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; CHECK: {{^}}.L[[propertyWrite_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: jsVoidCall:
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; CHECK: {{^}}.L[[jsVoidCall_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: jsIntCall:
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; CHECK: {{^}}.L[[jsIntCall_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: spilledValue:
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; CHECK: {{^}}.L[[spilledValue_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: spilledStackMapValue:
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; CHECK: {{^}}.L[[spilledStackMapValue_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: liveConstant:
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; CHECK: {{^}}.L[[liveConstant_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: clobberLR:
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; CHECK: {{^}}.L[[clobberLR_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: .section .llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 11
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; Num LargeConstants
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; CHECK-NEXT: .long 2
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; Num Callsites
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; CHECK-NEXT: .long 11
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; Functions and stack size
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; CHECK-NEXT: .quad constantargs
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad osrinline
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; CHECK-NEXT: .quad 144
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad osrcold
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad propertyRead
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad propertyWrite
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad jsVoidCall
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad jsIntCall
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad spilledValue
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; CHECK-NEXT: .quad 304
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad spilledStackMapValue
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; CHECK-NEXT: .quad 224
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad liveConstant
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; CHECK-NEXT: .quad 64
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad clobberLR
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; CHECK-NEXT: .quad 208
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; CHECK-NEXT: .quad 1
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; Num LargeConstants
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; CHECK-NEXT: .quad 4294967295
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; CHECK-NEXT: .quad 4294967296
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; Constant arguments
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;
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .long .L{{.*}}-.L[[constantargs_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 4
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 65535
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 65536
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; SmallConstant
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; LargeConstant at index 0
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 1
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define void @constantargs() {
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entry:
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%0 = inttoptr i64 244837814094590 to i8*
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tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 40, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
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ret void
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}
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; Inline OSR Exit
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;
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; CHECK: .long .L{{.*}}-.L[[osrinline_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @osrinline(i64 %a, i64 %b) {
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entry:
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; Runtime void->void call.
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call void inttoptr (i64 244837814094590 to void ()*)()
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; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
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call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
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ret void
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}
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; Cold OSR Exit
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;
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; 2 live variables in register.
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;
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; CHECK: .long .L{{.*}}-.L[[osrcold_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @osrcold(i64 %a, i64 %b) {
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entry:
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%test = icmp slt i64 %a, %b
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br i1 %test, label %ret, label %cold
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cold:
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; OSR patchpoint with 12-byte nop-slide and 2 live vars.
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%thunk = inttoptr i64 244837814094590 to i8*
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call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 40, i8* %thunk, i32 0, i64 %a, i64 %b)
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unreachable
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ret:
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ret void
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}
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; Property Read
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; CHECK: .long .L{{.*}}-.L[[propertyRead_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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;
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; FIXME: There are currently no stackmap entries. After moving to
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; AnyRegCC, we will have entries for the object and return value.
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define i64 @propertyRead(i64* %obj) {
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entry:
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%resolveRead = inttoptr i64 244837814094590 to i8*
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%result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %resolveRead, i32 1, i64* %obj)
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%add = add i64 %result, 3
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ret i64 %add
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}
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; Property Write
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; CHECK: .long .L{{.*}}-.L[[propertyWrite_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
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entry:
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%resolveWrite = inttoptr i64 244837814094590 to i8*
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call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 40, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
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ret void
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}
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; Void JS Call
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;
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; 2 live variables in registers.
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;
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; CHECK: .long .L{{.*}}-.L[[jsVoidCall_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
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entry:
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%resolveCall = inttoptr i64 244837814094590 to i8*
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call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
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ret void
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}
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; i64 JS Call
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;
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; 2 live variables in registers.
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;
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; CHECK: .long .L{{.*}}-.L[[jsIntCall_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
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entry:
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%resolveCall = inttoptr i64 244837814094590 to i8*
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%result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
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%add = add i64 %result, 3
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ret i64 %add
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}
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; Spilled stack map values.
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;
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; Verify 28 stack map entries.
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;
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; CHECK: .long .L{{.*}}-.L[[spilledValue_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 28
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;
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; Check that at least one is a spilled entry from r31.
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; Location: Indirect FP + ...
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; CHECK: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 31
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define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
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entry:
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call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 40, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
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ret void
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}
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; Spilled stack map values.
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;
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; Verify 30 stack map entries.
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;
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; CHECK: .long .L{{.*}}-.L[[spilledStackMapValue_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 30
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;
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; Check that at least one is a spilled entry from r31.
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; Location: Indirect FP + ...
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; CHECK: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 31
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define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
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entry:
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call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
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ret void
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}
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; Map a constant value.
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;
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; CHECK: .long .L{{.*}}-.L[[liveConstant_BEGIN]]
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; CHECK-NEXT: .short 0
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; 1 location
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; CHECK-NEXT: .short 1
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; Loc 0: SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 33
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define void @liveConstant() {
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
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ret void
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}
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; Map a value when LR is the only free register.
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;
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; CHECK: .long .L{{.*}}-.L[[clobberLR_BEGIN]]
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; CHECK-NEXT: .short 0
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; 1 location
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; CHECK-NEXT: .short 1
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; Loc 0: Indirect FP (r31) - offset
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short 31
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; CHECK-NEXT: .long {{[0-9]+}}
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define void @clobberLR(i32 %a) {
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tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
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tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
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ret void
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}
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declare void @llvm.experimental.stackmap(i64, i32, ...)
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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