forked from OSchip/llvm-project
272 lines
9.6 KiB
LLVM
272 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
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define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
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; CHECK-MVE-FP-LABEL: vfma16_v1:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfma16_v1:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfma16_v1:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
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; CHECK-MVE-NEXT: vpush {d8, d9, d10}
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; CHECK-MVE-NEXT: vmovx.f16 s13, s0
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; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmovx.f16 s12, s8
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; CHECK-MVE-NEXT: vmovx.f16 s14, s4
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; CHECK-MVE-NEXT: vmov.f32 s16, s1
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; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
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; CHECK-MVE-NEXT: vmov r1, s0
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; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
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; CHECK-MVE-NEXT: vmov r0, s13
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; CHECK-MVE-NEXT: vmov.16 q3[0], r1
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; CHECK-MVE-NEXT: vmov.16 q3[1], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s9
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; CHECK-MVE-NEXT: vmovx.f16 s18, s5
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; CHECK-MVE-NEXT: vmovx.f16 s20, s1
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; CHECK-MVE-NEXT: vmov.16 q3[2], r0
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; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s2
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
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; CHECK-MVE-NEXT: vmov.16 q3[3], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s10
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; CHECK-MVE-NEXT: vmovx.f16 s18, s6
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; CHECK-MVE-NEXT: vmovx.f16 s20, s2
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; CHECK-MVE-NEXT: vmov.16 q3[4], r0
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; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s3
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
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; CHECK-MVE-NEXT: vmovx.f16 s8, s11
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; CHECK-MVE-NEXT: vmovx.f16 s4, s7
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; CHECK-MVE-NEXT: vmovx.f16 s0, s3
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; CHECK-MVE-NEXT: vmov.16 q3[5], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmov.16 q3[6], r0
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; CHECK-MVE-NEXT: vmov r0, s0
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; CHECK-MVE-NEXT: vmov.16 q3[7], r0
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; CHECK-MVE-NEXT: vmov q0, q3
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; CHECK-MVE-NEXT: vpop {d8, d9, d10}
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <8 x half> %src2, %src3
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%1 = fadd <8 x half> %src1, %0
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ret <8 x half> %1
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}
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define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
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; CHECK-MVE-FP-LABEL: vfma16_v2:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q0
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfma16_v2:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfma16_v2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
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; CHECK-MVE-NEXT: vpush {d8, d9, d10}
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; CHECK-MVE-NEXT: vmovx.f16 s13, s0
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; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmovx.f16 s12, s8
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; CHECK-MVE-NEXT: vmovx.f16 s14, s4
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; CHECK-MVE-NEXT: vmov.f32 s16, s1
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; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
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; CHECK-MVE-NEXT: vmov r1, s0
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; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
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; CHECK-MVE-NEXT: vmov r0, s13
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; CHECK-MVE-NEXT: vmov.16 q3[0], r1
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; CHECK-MVE-NEXT: vmov.16 q3[1], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s9
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; CHECK-MVE-NEXT: vmovx.f16 s18, s5
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; CHECK-MVE-NEXT: vmovx.f16 s20, s1
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; CHECK-MVE-NEXT: vmov.16 q3[2], r0
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; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s2
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
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; CHECK-MVE-NEXT: vmov.16 q3[3], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s10
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; CHECK-MVE-NEXT: vmovx.f16 s18, s6
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; CHECK-MVE-NEXT: vmovx.f16 s20, s2
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; CHECK-MVE-NEXT: vmov.16 q3[4], r0
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; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s3
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
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; CHECK-MVE-NEXT: vmovx.f16 s8, s11
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; CHECK-MVE-NEXT: vmovx.f16 s4, s7
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; CHECK-MVE-NEXT: vmovx.f16 s0, s3
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; CHECK-MVE-NEXT: vmov.16 q3[5], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmov.16 q3[6], r0
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; CHECK-MVE-NEXT: vmov r0, s0
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; CHECK-MVE-NEXT: vmov.16 q3[7], r0
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; CHECK-MVE-NEXT: vmov q0, q3
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; CHECK-MVE-NEXT: vpop {d8, d9, d10}
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <8 x half> %src2, %src3
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%1 = fadd <8 x half> %0, %src1
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ret <8 x half> %1
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}
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define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
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; CHECK-MVE-FP-LABEL: vfms16:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfms16:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfms16:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
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; CHECK-MVE-NEXT: vpush {d8, d9, d10}
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; CHECK-MVE-NEXT: vmovx.f16 s13, s0
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; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmovx.f16 s12, s8
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; CHECK-MVE-NEXT: vmovx.f16 s14, s4
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; CHECK-MVE-NEXT: vmov.f32 s16, s1
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; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
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; CHECK-MVE-NEXT: vmov r1, s0
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; CHECK-MVE-NEXT: vmls.f16 s16, s5, s9
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; CHECK-MVE-NEXT: vmov r0, s13
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; CHECK-MVE-NEXT: vmov.16 q3[0], r1
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; CHECK-MVE-NEXT: vmov.16 q3[1], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s9
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; CHECK-MVE-NEXT: vmovx.f16 s18, s5
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; CHECK-MVE-NEXT: vmovx.f16 s20, s1
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; CHECK-MVE-NEXT: vmov.16 q3[2], r0
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; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s2
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmls.f16 s16, s6, s10
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; CHECK-MVE-NEXT: vmov.16 q3[3], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmovx.f16 s16, s10
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; CHECK-MVE-NEXT: vmovx.f16 s18, s6
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; CHECK-MVE-NEXT: vmovx.f16 s20, s2
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; CHECK-MVE-NEXT: vmov.16 q3[4], r0
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; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
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; CHECK-MVE-NEXT: vmov.f32 s16, s3
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; CHECK-MVE-NEXT: vmov r0, s20
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; CHECK-MVE-NEXT: vmls.f16 s16, s7, s11
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; CHECK-MVE-NEXT: vmovx.f16 s8, s11
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; CHECK-MVE-NEXT: vmovx.f16 s4, s7
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; CHECK-MVE-NEXT: vmovx.f16 s0, s3
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; CHECK-MVE-NEXT: vmov.16 q3[5], r0
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; CHECK-MVE-NEXT: vmov r0, s16
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; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
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; CHECK-MVE-NEXT: vmov.16 q3[6], r0
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; CHECK-MVE-NEXT: vmov r0, s0
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; CHECK-MVE-NEXT: vmov.16 q3[7], r0
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; CHECK-MVE-NEXT: vmov q0, q3
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; CHECK-MVE-NEXT: vpop {d8, d9, d10}
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <8 x half> %src2, %src3
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%1 = fsub <8 x half> %src1, %0
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ret <8 x half> %1
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}
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define arm_aapcs_vfpcc <4 x float> @vfma32_v1(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
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; CHECK-MVE-FP-LABEL: vfma32_v1:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfma32_v1:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfma32_v1:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
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; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
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; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
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; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <4 x float> %src2, %src3
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%1 = fadd <4 x float> %src1, %0
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ret <4 x float> %1
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}
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define arm_aapcs_vfpcc <4 x float> @vfma32_v2(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
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; CHECK-MVE-FP-LABEL: vfma32_v2:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vadd.f32 q0, q1, q0
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfma32_v2:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfma32_v2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
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; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
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; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
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; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <4 x float> %src2, %src3
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%1 = fadd <4 x float> %0, %src1
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ret <4 x float> %1
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}
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define arm_aapcs_vfpcc <4 x float> @vfms32(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
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; CHECK-MVE-FP-LABEL: vfms32:
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; CHECK-MVE-FP: @ %bb.0: @ %entry
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; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
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; CHECK-MVE-FP-NEXT: vsub.f32 q0, q0, q1
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; CHECK-MVE-FP-NEXT: bx lr
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;
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; CHECK-MVE-VMLA-LABEL: vfms32:
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; CHECK-MVE-VMLA: @ %bb.0: @ %entry
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; CHECK-MVE-VMLA-NEXT: vfms.f32 q0, q1, q2
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; CHECK-MVE-VMLA-NEXT: bx lr
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;
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; CHECK-MVE-LABEL: vfms32:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmls.f32 s3, s7, s11
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; CHECK-MVE-NEXT: vmls.f32 s2, s6, s10
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; CHECK-MVE-NEXT: vmls.f32 s1, s5, s9
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; CHECK-MVE-NEXT: vmls.f32 s0, s4, s8
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; CHECK-MVE-NEXT: bx lr
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entry:
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%0 = fmul <4 x float> %src2, %src3
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%1 = fsub <4 x float> %src1, %0
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ret <4 x float> %1
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}
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