forked from OSchip/llvm-project
067add7b5f
Implement vmsge{u}.vx pseudo instruction.
According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.
unmasked va >= x
pseudoinstruction: vmsge{u}.vx vd, va, x
expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
masked va >= x, vd != v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
masked va >= x, vd == v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt
Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.
Differential Revision: https://reviews.llvm.org/D84732
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| .. | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| RISCVAsmBackend.cpp | ||
| RISCVAsmBackend.h | ||
| RISCVELFObjectWriter.cpp | ||
| RISCVELFStreamer.cpp | ||
| RISCVELFStreamer.h | ||
| RISCVFixupKinds.h | ||
| RISCVInstPrinter.cpp | ||
| RISCVInstPrinter.h | ||
| RISCVMCAsmInfo.cpp | ||
| RISCVMCAsmInfo.h | ||
| RISCVMCCodeEmitter.cpp | ||
| RISCVMCExpr.cpp | ||
| RISCVMCExpr.h | ||
| RISCVMCTargetDesc.cpp | ||
| RISCVMCTargetDesc.h | ||
| RISCVTargetStreamer.cpp | ||
| RISCVTargetStreamer.h | ||