..
AsmParser
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
Disassembler
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
MCTargetDesc
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
TargetInfo
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Utils
Recommit "[RISCV] Remove include of RISCVRegisterInfo.h from RISCVBaseInfo.h. NFCI"
2020-11-01 10:35:37 -08:00
CMakeLists.txt
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
LLVMBuild.txt
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RISCV.h
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
RISCV.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Check all 64-bits of the mask in SelectRORIW.
2020-11-04 10:15:30 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add missing patterns for rotr with immediate for Zbb/Zbp extensions.
2020-11-03 10:04:52 -08:00
RISCVISelLowering.cpp
[RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled.
2020-11-05 10:46:45 -08:00
RISCVISelLowering.h
[RISCV] Optimize multiplication by constant
2020-07-07 18:50:24 -07:00
RISCVInstrFormats.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp
[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
2020-11-03 03:55:47 +00:00
RISCVInstrInfo.h
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
2020-09-21 10:21:11 +01:00
RISCVInstrInfo.td
[RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI
2020-11-04 09:59:14 -08:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[RISCV] Add isel patterns for fshl with immediate to select FSRI/FSRIW
2020-11-05 09:37:43 -08:00
RISCVInstrInfoC.td
[RISC-V] Mark C_MV as a move instruction
2020-08-27 10:32:23 +01:00
RISCVInstrInfoD.td
[RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first.
2020-11-05 14:00:25 -08:00
RISCVInstrInfoF.td
[RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first.
2020-11-05 14:00:25 -08:00
RISCVInstrInfoM.td
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RISCVInstrInfoV.td
[RISCV] fix a mistake in RISCVInstrInfoV.td
2020-10-15 23:16:53 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMachineFunctionInfo.h
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVMergeBaseOffset.cpp
[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
2020-09-03 20:01:23 +08:00
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSubtarget.h
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
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