forked from OSchip/llvm-project
231 lines
8.6 KiB
LLVM
231 lines
8.6 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}s_sext_i1_to_i32:
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; GCN: v_cndmask_b32_e64
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; GCN: s_endpgm
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define amdgpu_kernel void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%sext = sext i1 %cmp to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_s_sext_i32_to_i64:
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; GCN: s_ashr_i32
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; GCN: s_endpg
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define amdgpu_kernel void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%sext = sext i32 %add to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_i1_to_i64:
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; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
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; GCN: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%sext = sext i1 %cmp to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_i32_to_i64:
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; GCN: s_ashr_i32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind {
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%sext = sext i32 %a to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_i32_to_i64:
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; GCN: v_ashr
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; GCN: s_endpgm
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define amdgpu_kernel void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%sext = sext i32 %val to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_i16_to_i64:
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; GCN: s_load_dword [[VAL:s[0-9]+]]
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; GCN: s_bfe_i64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100000
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define amdgpu_kernel void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind {
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%sext = sext i16 %a to i64
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store i64 %sext, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_i1_to_i16:
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
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; GCN-NEXT: buffer_store_short [[RESULT]]
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define amdgpu_kernel void @s_sext_i1_to_i16(i16 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%sext = sext i1 %cmp to i16
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store i16 %sext, i16 addrspace(1)* %out
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ret void
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}
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; This purpose of this test is to make sure the i16 = sign_extend i1 node
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; makes it all the way throught the legalizer/optimizer to make sure
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; we select this correctly. In the s_sext_i1_to_i16, the sign_extend node
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; is optimized to a select very early.
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; GCN-LABEL: {{^}}s_sext_i1_to_i16_with_and:
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
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; GCN-NEXT: buffer_store_short [[RESULT]]
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define amdgpu_kernel void @s_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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%cmp0 = icmp eq i32 %a, %b
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%cmp1 = icmp eq i32 %c, %d
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%cmp = and i1 %cmp0, %cmp1
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%sext = sext i1 %cmp to i16
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store i16 %sext, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_i1_to_i16_with_and:
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1
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; GCN-NEXT: buffer_store_short [[RESULT]]
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define amdgpu_kernel void @v_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%cmp0 = icmp eq i32 %a, %tid
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%cmp1 = icmp eq i32 %b, %c
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%cmp = and i1 %cmp0, %cmp1
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%sext = sext i1 %cmp to i16
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store i16 %sext, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_sext_v4i8_to_v4i32:
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; GCN: s_load_dword [[VAL:s[0-9]+]]
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; GCN-DAG: s_bfe_i32 [[EXT2:s[0-9]+]], [[VAL]], 0x80010
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; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
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; SI-DAG: s_bfe_i32 [[EXT1:s[0-9]+]], [[VAL]], 0x80008
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; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]]
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; FIXME: We end up with a v_bfe instruction, because the i16 srl
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; gets selected to a v_lshrrev_b16 instructions, so the input to
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; the bfe is a vector registers. To fix this we need to be able to
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; optimize:
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; t29: i16 = truncate t10
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; t55: i16 = srl t29, Constant:i32<8>
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; t63: i32 = any_extend t55
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; t64: i32 = sign_extend_inreg t63, ValueType:ch:i8
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; VI-DAG: v_bfe_i32 [[VEXT1:v[0-9]+]], v{{[0-9]+}}, 0, 8
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; GCN-DAG: v_mov_b32_e32 [[VEXT0:v[0-9]+]], [[EXT0]]
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; SI-DAG: v_mov_b32_e32 [[VEXT1:v[0-9]+]], [[EXT1]]
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; GCN-DAG: v_mov_b32_e32 [[VEXT2:v[0-9]+]], [[EXT2]]
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; GCN-DAG: v_mov_b32_e32 [[VEXT3:v[0-9]+]], [[EXT3]]
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; GCN-DAG: buffer_store_dword [[VEXT0]]
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; GCN-DAG: buffer_store_dword [[VEXT1]]
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; GCN-DAG: buffer_store_dword [[VEXT2]]
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; GCN-DAG: buffer_store_dword [[VEXT3]]
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; GCN: s_endpgm
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define amdgpu_kernel void @s_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 %a) nounwind {
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%cast = bitcast i32 %a to <4 x i8>
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%ext = sext <4 x i8> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_v4i8_to_v4i32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; FIXME: need to optimize same sequence as above test to avoid
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; this shift.
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; VI-DAG: v_lshrrev_b16_e32 [[SH16:v[0-9]+]], 8, [[VAL]]
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; GCN-DAG: v_ashrrev_i32_e32 [[EXT3:v[0-9]+]], 24, [[VAL]]
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; VI-DAG: v_bfe_i32 [[EXT0:v[0-9]+]], [[VAL]], 0, 8
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; VI-DAG: v_bfe_i32 [[EXT2:v[0-9]+]], [[VAL]], 16, 8
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; VI-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[SH16]], 0, 8
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; SI-DAG: v_bfe_i32 [[EXT2:v[0-9]+]], [[VAL]], 16, 8
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; SI-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[VAL]], 8, 8
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; SI: v_bfe_i32 [[EXT0:v[0-9]+]], [[VAL]], 0, 8
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; GCN: buffer_store_dword [[EXT0]]
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; GCN: buffer_store_dword [[EXT1]]
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; GCN: buffer_store_dword [[EXT2]]
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; GCN: buffer_store_dword [[EXT3]]
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define amdgpu_kernel void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%a = load i32, i32 addrspace(1)* %in
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%cast = bitcast i32 %a to <4 x i8>
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%ext = sext <4 x i8> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: s_bfe_i64, same on SI and VI
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; GCN-LABEL: {{^}}s_sext_v4i16_to_v4i32:
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; SI-DAG: s_ashr_i64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 48
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; SI-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; VI: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; VI: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; GCN-DAG: s_sext_i32_i16
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; GCN-DAG: s_sext_i32_i16
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; GCN: s_endpgm
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define amdgpu_kernel void @s_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 %a) nounwind {
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%cast = bitcast i64 %a to <4 x i16>
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%ext = sext <4 x i16> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sext_v4i16_to_v4i32:
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; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; GCN: s_endpgm
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define amdgpu_kernel void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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%a = load i64, i64 addrspace(1)* %in
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%cast = bitcast i64 %a to <4 x i16>
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%ext = sext <4 x i16> %cast to <4 x i32>
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%elt0 = extractelement <4 x i32> %ext, i32 0
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%elt1 = extractelement <4 x i32> %ext, i32 1
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%elt2 = extractelement <4 x i32> %ext, i32 2
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%elt3 = extractelement <4 x i32> %ext, i32 3
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store volatile i32 %elt0, i32 addrspace(1)* %out
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store volatile i32 %elt1, i32 addrspace(1)* %out
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store volatile i32 %elt2, i32 addrspace(1)* %out
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store volatile i32 %elt3, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #1 = { nounwind readnone }
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