forked from OSchip/llvm-project
185 lines
6.7 KiB
LLVM
185 lines
6.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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declare float @llvm.fabs.f32(float) #1
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declare double @llvm.fabs.f64(double) #1
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; GCN-LABEL: {{^}}test_isinf_pattern:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
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; GCN: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; GCN-NOT: v_cmp
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_not_isinf_pattern_0:
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; GCN-NOT: v_cmp_class
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; GCN: s_endpgm
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define amdgpu_kernel void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp ueq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_not_isinf_pattern_1:
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; GCN-NOT: v_cmp_class
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; GCN: s_endpgm
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define amdgpu_kernel void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0xFFF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_isfinite_pattern_0:
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; GCN-NOT: v_cmp
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
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; GCN: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; GCN-NOT: v_cmp
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isfinite_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_isfinite_pattern_1:
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; SI-NOT: v_cmp
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; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
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; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; SI-NOT: v_cmp
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; SI: s_endpgm
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define amdgpu_kernel void @test_isfinite_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #3
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%cmpinf = fcmp one float %x.fabs, 0x7FF0000000000000
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%ext = zext i1 %cmpinf to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Use negative infinity
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; GCN-LABEL: {{^}}test_isfinite_not_pattern_0:
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; GCN-NOT: v_cmp_class_f32
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isfinite_not_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0xFFF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; No fabs
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; GCN-LABEL: {{^}}test_isfinite_not_pattern_1:
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; GCN-NOT: v_cmp_class_f32
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isfinite_not_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%ninf = fcmp une float %x, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; fabs of different value
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; GCN-LABEL: {{^}}test_isfinite_not_pattern_2:
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; GCN-NOT: v_cmp_class_f32
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isfinite_not_pattern_2(i32 addrspace(1)* nocapture %out, float %x, float %y) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %y) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; Wrong ordered compare type
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; GCN-LABEL: {{^}}test_isfinite_not_pattern_3:
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; GCN-NOT: v_cmp_class_f32
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; GCN: s_endpgm
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define amdgpu_kernel void @test_isfinite_not_pattern_3(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp uno float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp une float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_isfinite_pattern_4:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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define amdgpu_kernel void @test_isfinite_pattern_4(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_isfinite_pattern_4_commute_and:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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define amdgpu_kernel void @test_isfinite_pattern_4_commute_and(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%ord = fcmp ord float %x, 0.000000e+00
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ninf, %ord
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_not_isfinite_pattern_4_wrong_ord_test:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x14|0x50}}
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1f8
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; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
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; SI-DAG: v_cmp_o_f32_e32 vcc, [[X]], [[VY]]
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; SI-DAG: v_cmp_class_f32_e64 [[CLASS:s\[[0-9]+:[0-9]+\]]], [[X]], [[K]]
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; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CLASS]]
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; VI-DAG: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[X]], [[VY]]
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; VI-DAG: v_cmp_class_f32_e32 vcc, [[X]], [[K]]
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; VI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP]], vcc
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[AND]]
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define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(i32 addrspace(1)* nocapture %out, float %x, [8 x i32], float %y) #0 {
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%ord = fcmp ord float %x, %y
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%x.fabs = tail call float @llvm.fabs.f32(float %x) #1
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%ninf = fcmp one float %x.fabs, 0x7FF0000000000000
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%and = and i1 %ord, %ninf
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%ext = zext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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