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llvm-project/llvm/test/CodeGen/MIR
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Francis Visoiu Mistrih 93ef145862 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
 		2017-11-30 12:12:19 +00:00
..
AArch64 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
AMDGPU MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
ARM [IfConversion] Add testcases [NFC] 2017-09-20 08:23:29 +00:00
Generic [RegAllocFast] Add the proper initialize method to use the .mir infrastructure 2017-07-07 19:25:42 +00:00
Hexagon [Hexagon] Handle Hexagon-specific machine operand target flags in MIR 2017-07-10 18:31:02 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
PowerPC MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. 2016-08-24 01:32:41 +00:00
X86 Control-Flow Enforcement Technology - Shadow Stack support (LLVM side) 2017-11-26 13:02:45 +00:00
README Add README describing the intention of test/CodeGen/MIR 2016-12-09 20:16:12 +00:00

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.