forked from OSchip/llvm-project
89 lines
2.8 KiB
C++
89 lines
2.8 KiB
C++
//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the RISCV target.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-isel"
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// RISCV-specific code to select RISCV machine instructions for
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// SelectionDAG operations.
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namespace {
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class RISCVDAGToDAGISel final : public SelectionDAGISel {
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const RISCVSubtarget *Subtarget;
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public:
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explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
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: SelectionDAGISel(TargetMachine) {}
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StringRef getPassName() const override {
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return "RISCV DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<RISCVSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *Node) override;
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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};
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}
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void RISCVDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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MVT XLenVT = Subtarget->getXLenVT();
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// Dump information about the Node being selected.
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DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << "\n");
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// If we have a custom node, we have already selected
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if (Node->isMachineOpcode()) {
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DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
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Node->setNodeId(-1);
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return;
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}
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// Instruction Selection not handled by the auto-generated tablegen selection
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// should be handled here.
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EVT VT = Node->getValueType(0);
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if (Opcode == ISD::Constant && VT == XLenVT) {
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auto *ConstNode = cast<ConstantSDNode>(Node);
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// Materialize zero constants as copies from X0. This allows the coalescer
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// to propagate these into other instructions.
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if (ConstNode->isNullValue()) {
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SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
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RISCV::X0, XLenVT);
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ReplaceNode(Node, New.getNode());
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return;
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}
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}
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// Select the default instruction.
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SelectCode(Node);
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}
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// This pass converts a legalized DAG into a RISCV-specific DAG, ready
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// for instruction scheduling.
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FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) {
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return new RISCVDAGToDAGISel(TM);
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}
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