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llvm-project/llvm/lib/Target/Hexagon
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Francis Visoiu Mistrih 93ef145862 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
 		2017-11-30 12:12:19 +00:00
..
AsmParser [Asm] Add debug tracing in table-generated assembly matcher 2017-10-11 09:17:43 +00:00
Disassembler Hexagon: Fold a single-use textual header into its use 2017-10-25 19:52:21 +00:00
MCTargetDesc [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering 2017-11-28 20:48:10 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
BitTracker.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
BitTracker.h [Hexagon] Better determination of register classes in bit tracker 2017-09-25 19:12:55 +00:00
CMakeLists.txt [Hexagon] Reorganize and update instruction patterns 2017-10-20 19:33:12 +00:00
Hexagon.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
Hexagon.td [Hexagon] Reorganize and update instruction patterns 2017-10-20 19:33:12 +00:00
HexagonAsmPrinter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonAsmPrinter.h [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
HexagonBitSimplify.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonBitTracker.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
HexagonBitTracker.h [Hexagon] Better determination of register classes in bit tracker 2017-09-25 19:12:55 +00:00
HexagonBlockRanges.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonBlockRanges.h [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-09-28 22:27:31 +00:00
HexagonBranchRelaxation.cpp
…
HexagonCFGOptimizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonCommonGEP.cpp [Hexagon] Fix expensive checks build bot broken in r309230. 2017-07-26 23:56:29 +00:00
HexagonConstExtenders.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
HexagonConstPropagation.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonCopyToCombine.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
HexagonDepArch.h [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC) 2017-10-18 17:45:22 +00:00
HexagonDepArch.td [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC) 2017-10-18 17:45:22 +00:00
HexagonDepIICHVX.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonDepIICScalar.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonDepITypes.h [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonDepITypes.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonDepInstrFormats.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonDepInstrInfo.td [Hexagon] Mark vector loads as predicable, update instruction mappings 2017-10-18 17:36:46 +00:00
HexagonDepMappings.td [Hexagon] Switch to parameterized register classes for HVX 2017-09-15 15:46:05 +00:00
HexagonDepOperands.td [Hexagon] Change the vector scaling for vector offsets 2017-04-06 17:28:21 +00:00
HexagonDepTimingClasses.h HexagonDepTimingClasses.h: Don't mark header functions as file local 2017-10-24 21:29:16 +00:00
HexagonEarlyIfConv.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonExpandCondsets.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonFixupHwLoops.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
HexagonFrameLowering.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
HexagonFrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
HexagonGenExtract.cpp [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-09-28 22:27:31 +00:00
HexagonGenInsert.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonGenMux.cpp [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-29 00:56:56 +00:00
HexagonGenPredicate.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
HexagonHardwareLoops.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonHazardRecognizer.cpp
…
HexagonHazardRecognizer.h
…
HexagonIICHVX.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonIICScalar.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonISelDAGToDAG.cpp Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC 2017-11-10 20:09:46 +00:00
HexagonISelDAGToDAG.h Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC 2017-11-10 20:09:46 +00:00
HexagonISelLowering.cpp [Hexagon] Remove HexagonISD::PACKHL 2017-11-29 19:59:29 +00:00
HexagonISelLowering.h [Hexagon] Remove HexagonISD::PACKHL 2017-11-29 19:59:29 +00:00
HexagonInstrFormats.td [Hexagon] Switch to parameterized register classes for HVX 2017-09-15 15:46:05 +00:00
HexagonInstrFormatsV4.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonInstrFormatsV60.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonInstrInfo.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
HexagonInstrInfo.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
HexagonIntrinsics.td [Hexagon] Switch to parameterized register classes for HVX 2017-09-15 15:46:05 +00:00
HexagonIntrinsicsV3.td
…
HexagonIntrinsicsV4.td
…
HexagonIntrinsicsV5.td
…
HexagonIntrinsicsV60.td [Hexagon] Switch to parameterized register classes for HVX 2017-09-15 15:46:05 +00:00
HexagonLoopIdiomRecognition.cpp Use getStoreSize() in various places instead of 'BitSize >> 3'. 2017-11-28 14:44:32 +00:00
HexagonMCInstLower.cpp [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
HexagonMachineFunctionInfo.cpp
…
HexagonMachineFunctionInfo.h [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-04 02:02:05 +00:00
HexagonMachineScheduler.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonMachineScheduler.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonMapAsm2IntrinV62.gen.td [Hexagon] Switch to parameterized register classes for HVX 2017-09-15 15:46:05 +00:00
HexagonNewValueJump.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
HexagonOperands.td [Hexagon] Reorganize and update instruction patterns 2017-10-20 19:33:12 +00:00
HexagonOptAddrMode.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonOptimizeSZextends.cpp
…
HexagonPatterns.td [Hexagon] Remove HexagonISD::PACKHL 2017-11-29 19:59:29 +00:00
HexagonPeephole.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonPseudo.td [Hexagon] New HVX target features. 2017-10-18 18:07:07 +00:00
HexagonRDFOpt.cpp [Hexagon] Allow the RDF optimizations to be run in .mir testcases 2017-10-30 14:11:52 +00:00
HexagonRegisterInfo.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
HexagonRegisterInfo.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonRegisterInfo.td [Hexagon] Remove trailing spaces, NFC 2017-11-22 20:43:00 +00:00
HexagonSchedule.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonScheduleV4.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonScheduleV55.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonScheduleV60.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonScheduleV62.td [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
HexagonSelectionDAGInfo.cpp Make library calls sensitive to regparm module flag (Fixes PR3997). 2017-03-18 00:44:07 +00:00
HexagonSelectionDAGInfo.h
…
HexagonSplitConst32AndConst64.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
HexagonSplitDouble.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
HexagonStoreWidening.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonSubtarget.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
HexagonSubtarget.h [Hexagon] Implement HexagonSubtarget::isHVXVectorType 2017-11-27 18:12:16 +00:00
HexagonTargetMachine.cpp [Hexagon] Allow the RDF optimizations to be run in .mir testcases 2017-10-30 14:11:52 +00:00
HexagonTargetMachine.h Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00
HexagonTargetObjectFile.cpp [Hexagon] Emit lookup tables in text section based on a flag 2017-07-18 15:31:37 +00:00
HexagonTargetObjectFile.h [Hexagon] Emit lookup tables in text section based on a flag 2017-07-18 15:31:37 +00:00
HexagonTargetStreamer.h
…
HexagonTargetTransformInfo.cpp [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
HexagonTargetTransformInfo.h [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
HexagonVLIWPacketizer.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
HexagonVLIWPacketizer.h [Pipeliner] Improve serialization order for post-increments 2017-10-11 15:51:44 +00:00
HexagonVectorLoopCarriedReuse.cpp Add llvm::for_each as a range-based extensions to <algorithm> and make use of it in some cases where it is a more clear alternative to std::for_each. 2017-11-03 20:01:25 +00:00
HexagonVectorPrint.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LLVMBuild.txt [Hexagon] Require IPO library in Hexagon build 2017-01-26 23:03:22 +00:00
RDFCopy.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
RDFCopy.h [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
RDFDeadCode.cpp [Hexagon] Make sure that RDF does not remove EH_LABELs 2017-11-21 21:05:51 +00:00
RDFDeadCode.h
…
RDFGraph.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
RDFGraph.h [RDF] Simplify construction of maximal registers 2017-10-05 17:12:49 +00:00
RDFLiveness.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RDFLiveness.h [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-01 21:20:10 +00:00
RDFRegisters.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RDFRegisters.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00