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Ian Bearman 0816b96a10 Allow same memory space for SRC and DST of dma_start operations 
This change allows the SRC and DST of dma_start operations to be located in the
    same memory space. This applies to both the Affine dialect and Memref dialect
    versions of these Ops. The documention has been updated to reflect this by
    explicitly stating overlapping memory locations are not supported (undefined
    behavior).

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D102274
 		2021-05-14 10:40:15 -07:00
..
cmake/modules [cmake] Add support for multiple distributions 2021-05-12 11:13:18 -07:00
docs [mlir][tosa] Remove tosa.identityn operator 2021-05-12 12:46:22 -07:00
examples [mlir] Support alignment in LLVM dialect GlobalOp 2021-05-12 09:07:20 +02:00
include Allow same memory space for SRC and DST of dma_start operations 2021-05-14 10:40:15 -07:00
lib Allow same memory space for SRC and DST of dma_start operations 2021-05-14 10:40:15 -07:00
python [mlir][sparse][capi][python] add sparse tensor passes 2021-05-12 16:40:50 -07:00
test Allow same memory space for SRC and DST of dma_start operations 2021-05-14 10:40:15 -07:00
tools [mlir][NFC] Move passes in test/lib/Transforms/ to a directory that mirrors what they test 2021-05-14 10:28:11 -07:00
unittests [mlir][spirv] NFC: Replace OwningSPIRVModuleRef with OwningOpRef 2021-05-06 17:17:44 -04:00
utils [mlir] Add a vscode language extension for MLIR 2021-04-21 14:44:37 -07:00
.clang-format
…
.clang-tidy Fix MLIR clang-tidy: when tweaking it does not inherit from the parent 2020-03-07 17:44:21 +00:00
CMakeLists.txt Move MLIR python sources to mlir/python. 2021-05-03 18:36:48 +00:00
LICENSE.TXT Add the Apache2 with LLVM exceptions license to MLIR 2019-12-24 00:58:06 -08:00
README.md mlir README.md: Fix the syntax 2019-12-24 13:31:07 +01:00

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.