forked from OSchip/llvm-project
60aa646441
This adds a G_ASSERT_SEXT opcode, similar to G_ASSERT_ZEXT. This instruction
signifies that an operation was already sign extended from a smaller type.
This is useful for functions with sign-extended parameters.
E.g.
```
define void @foo(i16 signext %x) {
...
}
```
This adds verifier, regbankselect, and instruction selection support for
G_ASSERT_SEXT equivalent to G_ASSERT_ZEXT.
Differential Revision: https://reviews.llvm.org/D96890
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|---|---|---|
| .. | ||
| GMIR.rst | ||
| GenericOpcode.rst | ||
| IRTranslator.rst | ||
| InstructionSelect.rst | ||
| KnownBits.rst | ||
| Legalizer.rst | ||
| Pipeline.rst | ||
| Porting.rst | ||
| RegBankSelect.rst | ||
| Resources.rst | ||
| block-extract.png | ||
| index.rst | ||
| pipeline-overview-customized.png | ||
| pipeline-overview-with-combiners.png | ||
| pipeline-overview.png | ||
| testing-pass-level.png | ||
| testing-unit-level.png | ||
