forked from OSchip/llvm-project
607 lines
22 KiB
C++
607 lines
22 KiB
C++
//===- LiveRangeCalc.cpp - Calculate live ranges --------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the LiveRangeCalc class.
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//
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//===----------------------------------------------------------------------===//
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#include "LiveRangeCalc.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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#include <tuple>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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// Reserve an address that indicates a value that is known to be "undef".
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static VNInfo UndefVNI(0xbad, SlotIndex());
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void LiveRangeCalc::resetLiveOutMap() {
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unsigned NumBlocks = MF->getNumBlockIDs();
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Seen.clear();
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Seen.resize(NumBlocks);
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EntryInfos.clear();
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Map.resize(NumBlocks);
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}
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void LiveRangeCalc::reset(const MachineFunction *mf,
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SlotIndexes *SI,
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MachineDominatorTree *MDT,
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VNInfo::Allocator *VNIA) {
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MF = mf;
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MRI = &MF->getRegInfo();
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Indexes = SI;
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DomTree = MDT;
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Alloc = VNIA;
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resetLiveOutMap();
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LiveIn.clear();
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}
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static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
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LiveRange &LR, const MachineOperand &MO) {
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const MachineInstr &MI = *MO.getParent();
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SlotIndex DefIdx =
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Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
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// Create the def in LR. This may find an existing def.
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LR.createDeadDef(DefIdx, Alloc);
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}
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void LiveRangeCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
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assert(MRI && Indexes && "call reset() first");
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// Step 1: Create minimal live segments for every definition of Reg.
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// Visit all def operands. If the same instruction has multiple defs of Reg,
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// createDeadDef() will deduplicate.
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const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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unsigned Reg = LI.reg;
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for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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if (!MO.isDef() && !MO.readsReg())
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continue;
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unsigned SubReg = MO.getSubReg();
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if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
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LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
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: MRI->getMaxLaneMaskForVReg(Reg);
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// If this is the first time we see a subregister def, initialize
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// subranges by creating a copy of the main range.
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if (!LI.hasSubRanges() && !LI.empty()) {
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LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
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LI.createSubRangeFrom(*Alloc, ClassMask, LI);
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}
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LI.refineSubRanges(*Alloc, SubMask,
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[&MO, this](LiveInterval::SubRange &SR) {
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if (MO.isDef())
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createDeadDef(*Indexes, *Alloc, SR, MO);
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},
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*Indexes, TRI);
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}
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// Create the def in the main liverange. We do not have to do this if
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// subranges are tracked as we recreate the main range later in this case.
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if (MO.isDef() && !LI.hasSubRanges())
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createDeadDef(*Indexes, *Alloc, LI, MO);
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}
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// We may have created empty live ranges for partially undefined uses, we
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// can't keep them because we won't find defs in them later.
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LI.removeEmptySubRanges();
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// Step 2: Extend live segments to all uses, constructing SSA form as
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// necessary.
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if (LI.hasSubRanges()) {
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for (LiveInterval::SubRange &S : LI.subranges()) {
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LiveRangeCalc SubLRC;
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SubLRC.reset(MF, Indexes, DomTree, Alloc);
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SubLRC.extendToUses(S, Reg, S.LaneMask, &LI);
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}
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LI.clear();
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constructMainRangeFromSubranges(LI);
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} else {
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resetLiveOutMap();
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extendToUses(LI, Reg, LaneBitmask::getAll());
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}
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}
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void LiveRangeCalc::constructMainRangeFromSubranges(LiveInterval &LI) {
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// First create dead defs at all defs found in subranges.
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LiveRange &MainRange = LI;
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assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
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"Expect empty main liverange");
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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for (const VNInfo *VNI : SR.valnos) {
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if (!VNI->isUnused() && !VNI->isPHIDef())
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MainRange.createDeadDef(VNI->def, *Alloc);
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}
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}
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resetLiveOutMap();
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extendToUses(MainRange, LI.reg, LaneBitmask::getAll(), &LI);
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}
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void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
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assert(MRI && Indexes && "call reset() first");
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// Visit all def operands. If the same instruction has multiple defs of Reg,
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// LR.createDeadDef() will deduplicate.
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for (MachineOperand &MO : MRI->def_operands(Reg))
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createDeadDef(*Indexes, *Alloc, LR, MO);
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}
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void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask Mask,
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LiveInterval *LI) {
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SmallVector<SlotIndex, 4> Undefs;
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if (LI != nullptr)
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LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
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// Visit all operands that read Reg. This may include partial defs.
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bool IsSubRange = !Mask.all();
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const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
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for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
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// Clear all kill flags. They will be reinserted after register allocation
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// by LiveIntervals::addKillFlags().
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if (MO.isUse())
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MO.setIsKill(false);
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// MO::readsReg returns "true" for subregister defs. This is for keeping
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// liveness of the entire register (i.e. for the main range of the live
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// interval). For subranges, definitions of non-overlapping subregisters
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// do not count as uses.
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if (!MO.readsReg() || (IsSubRange && MO.isDef()))
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continue;
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unsigned SubReg = MO.getSubReg();
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if (SubReg != 0) {
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LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
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if (MO.isDef())
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SLM = ~SLM;
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// Ignore uses not reading the current (sub)range.
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if ((SLM & Mask).none())
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continue;
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}
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// Determine the actual place of the use.
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const MachineInstr *MI = MO.getParent();
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unsigned OpNo = (&MO - &MI->getOperand(0));
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SlotIndex UseIdx;
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if (MI->isPHI()) {
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assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
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// The actual place where a phi operand is used is the end of the pred
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// MBB. PHI operands are paired: (Reg, PredMBB).
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UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
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} else {
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// Check for early-clobber redefs.
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bool isEarlyClobber = false;
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unsigned DefIdx;
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if (MO.isDef())
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isEarlyClobber = MO.isEarlyClobber();
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else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
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// FIXME: This would be a lot easier if tied early-clobber uses also
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// had an early-clobber flag.
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isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
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}
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UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
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}
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// MI is reading Reg. We may have visited MI before if it happens to be
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// reading Reg multiple times. That is OK, extend() is idempotent.
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extend(LR, UseIdx, Reg, Undefs);
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}
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}
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void LiveRangeCalc::updateFromLiveIns() {
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LiveRangeUpdater Updater;
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for (const LiveInBlock &I : LiveIn) {
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if (!I.DomNode)
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continue;
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MachineBasicBlock *MBB = I.DomNode->getBlock();
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assert(I.Value && "No live-in value found");
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(MBB);
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if (I.Kill.isValid())
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// Value is killed inside this block.
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End = I.Kill;
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else {
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// The value is live-through, update LiveOut as well.
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// Defer the Domtree lookup until it is needed.
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assert(Seen.test(MBB->getNumber()));
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Map[MBB] = LiveOutPair(I.Value, nullptr);
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}
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Updater.setDest(&I.LR);
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Updater.add(Start, End, I.Value);
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}
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LiveIn.clear();
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}
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void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
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ArrayRef<SlotIndex> Undefs) {
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assert(Use.isValid() && "Invalid SlotIndex");
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assert(Indexes && "Missing SlotIndexes");
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assert(DomTree && "Missing dominator tree");
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MachineBasicBlock *UseMBB = Indexes->getMBBFromIndex(Use.getPrevSlot());
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assert(UseMBB && "No MBB at Use");
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// Is there a def in the same MBB we can extend?
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auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use);
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if (EP.first != nullptr || EP.second)
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return;
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// Find the single reaching def, or determine if Use is jointly dominated by
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// multiple values, and we may need to create even more phi-defs to preserve
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// VNInfo SSA form. Perform a search for all predecessor blocks where we
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// know the dominating VNInfo.
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if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs))
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return;
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// When there were multiple different values, we may need new PHIs.
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calculateValues();
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}
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// This function is called by a client after using the low-level API to add
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// live-out and live-in blocks. The unique value optimization is not
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// available, SplitEditor::transferValues handles that case directly anyway.
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void LiveRangeCalc::calculateValues() {
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assert(Indexes && "Missing SlotIndexes");
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assert(DomTree && "Missing dominator tree");
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updateSSA();
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updateFromLiveIns();
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}
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bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
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MachineBasicBlock &MBB, BitVector &DefOnEntry,
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BitVector &UndefOnEntry) {
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unsigned BN = MBB.getNumber();
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if (DefOnEntry[BN])
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return true;
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if (UndefOnEntry[BN])
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return false;
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auto MarkDefined = [BN, &DefOnEntry](MachineBasicBlock &B) -> bool {
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for (MachineBasicBlock *S : B.successors())
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DefOnEntry[S->getNumber()] = true;
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DefOnEntry[BN] = true;
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return true;
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};
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SetVector<unsigned> WorkList;
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// Checking if the entry of MBB is reached by some def: add all predecessors
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// that are potentially defined-on-exit to the work list.
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for (MachineBasicBlock *P : MBB.predecessors())
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WorkList.insert(P->getNumber());
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for (unsigned i = 0; i != WorkList.size(); ++i) {
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// Determine if the exit from the block is reached by some def.
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unsigned N = WorkList[i];
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MachineBasicBlock &B = *MF->getBlockNumbered(N);
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if (Seen[N]) {
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const LiveOutPair &LOB = Map[&B];
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if (LOB.first != nullptr && LOB.first != &UndefVNI)
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return MarkDefined(B);
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}
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SlotIndex Begin, End;
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std::tie(Begin, End) = Indexes->getMBBRange(&B);
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// Treat End as not belonging to B.
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// If LR has a segment S that starts at the next block, i.e. [End, ...),
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// std::upper_bound will return the segment following S. Instead,
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// S should be treated as the first segment that does not overlap B.
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LiveRange::iterator UB = std::upper_bound(LR.begin(), LR.end(),
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End.getPrevSlot());
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if (UB != LR.begin()) {
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LiveRange::Segment &Seg = *std::prev(UB);
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if (Seg.end > Begin) {
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// There is a segment that overlaps B. If the range is not explicitly
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// undefined between the end of the segment and the end of the block,
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// treat the block as defined on exit. If it is, go to the next block
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// on the work list.
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if (LR.isUndefIn(Undefs, Seg.end, End))
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continue;
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return MarkDefined(B);
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}
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}
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// No segment overlaps with this block. If this block is not defined on
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// entry, or it undefines the range, do not process its predecessors.
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if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) {
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UndefOnEntry[N] = true;
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continue;
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}
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if (DefOnEntry[N])
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return MarkDefined(B);
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// Still don't know: add all predecessors to the work list.
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for (MachineBasicBlock *P : B.predecessors())
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WorkList.insert(P->getNumber());
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}
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UndefOnEntry[BN] = true;
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return false;
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}
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bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
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SlotIndex Use, unsigned PhysReg,
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ArrayRef<SlotIndex> Undefs) {
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unsigned UseMBBNum = UseMBB.getNumber();
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// Block numbers where LR should be live-in.
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SmallVector<unsigned, 16> WorkList(1, UseMBBNum);
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// Remember if we have seen more than one value.
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bool UniqueVNI = true;
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VNInfo *TheVNI = nullptr;
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bool FoundUndef = false;
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// Using Seen as a visited set, perform a BFS for all reaching defs.
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for (unsigned i = 0; i != WorkList.size(); ++i) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
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#ifndef NDEBUG
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if (MBB->pred_empty()) {
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MBB->getParent()->verify();
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errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo())
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<< " does not have a corresponding definition on every path:\n";
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const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
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if (MI != nullptr)
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errs() << Use << " " << *MI;
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report_fatal_error("Use not jointly dominated by defs.");
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}
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if (Register::isPhysicalRegister(PhysReg) && !MBB->isLiveIn(PhysReg)) {
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MBB->getParent()->verify();
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const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
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errs() << "The register " << printReg(PhysReg, TRI)
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<< " needs to be live in to " << printMBBReference(*MBB)
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<< ", but is missing from the live-in list.\n";
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report_fatal_error("Invalid global physical register");
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}
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#endif
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FoundUndef |= MBB->pred_empty();
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for (MachineBasicBlock *Pred : MBB->predecessors()) {
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// Is this a known live-out block?
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if (Seen.test(Pred->getNumber())) {
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if (VNInfo *VNI = Map[Pred].first) {
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if (TheVNI && TheVNI != VNI)
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UniqueVNI = false;
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TheVNI = VNI;
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}
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continue;
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}
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(Pred);
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// First time we see Pred. Try to determine the live-out value, but set
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// it as null if Pred is live-through with an unknown value.
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auto EP = LR.extendInBlock(Undefs, Start, End);
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VNInfo *VNI = EP.first;
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FoundUndef |= EP.second;
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setLiveOutValue(Pred, EP.second ? &UndefVNI : VNI);
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if (VNI) {
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if (TheVNI && TheVNI != VNI)
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UniqueVNI = false;
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TheVNI = VNI;
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}
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if (VNI || EP.second)
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continue;
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// No, we need a live-in value for Pred as well
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if (Pred != &UseMBB)
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WorkList.push_back(Pred->getNumber());
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else
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// Loopback to UseMBB, so value is really live through.
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Use = SlotIndex();
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}
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}
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LiveIn.clear();
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FoundUndef |= (TheVNI == nullptr || TheVNI == &UndefVNI);
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if (!Undefs.empty() && FoundUndef)
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UniqueVNI = false;
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// Both updateSSA() and LiveRangeUpdater benefit from ordered blocks, but
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// neither require it. Skip the sorting overhead for small updates.
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if (WorkList.size() > 4)
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array_pod_sort(WorkList.begin(), WorkList.end());
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// If a unique reaching def was found, blit in the live ranges immediately.
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if (UniqueVNI) {
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assert(TheVNI != nullptr && TheVNI != &UndefVNI);
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LiveRangeUpdater Updater(&LR);
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for (unsigned BN : WorkList) {
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SlotIndex Start, End;
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std::tie(Start, End) = Indexes->getMBBRange(BN);
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// Trim the live range in UseMBB.
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if (BN == UseMBBNum && Use.isValid())
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End = Use;
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else
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Map[MF->getBlockNumbered(BN)] = LiveOutPair(TheVNI, nullptr);
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Updater.add(Start, End, TheVNI);
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}
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return true;
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}
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// Prepare the defined/undefined bit vectors.
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EntryInfoMap::iterator Entry;
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bool DidInsert;
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std::tie(Entry, DidInsert) = EntryInfos.insert(
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std::make_pair(&LR, std::make_pair(BitVector(), BitVector())));
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if (DidInsert) {
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// Initialize newly inserted entries.
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unsigned N = MF->getNumBlockIDs();
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Entry->second.first.resize(N);
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Entry->second.second.resize(N);
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}
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BitVector &DefOnEntry = Entry->second.first;
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BitVector &UndefOnEntry = Entry->second.second;
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// Multiple values were found, so transfer the work list to the LiveIn array
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// where UpdateSSA will use it as a work list.
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LiveIn.reserve(WorkList.size());
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for (unsigned BN : WorkList) {
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|
MachineBasicBlock *MBB = MF->getBlockNumbered(BN);
|
|
if (!Undefs.empty() &&
|
|
!isDefOnEntry(LR, Undefs, *MBB, DefOnEntry, UndefOnEntry))
|
|
continue;
|
|
addLiveInBlock(LR, DomTree->getNode(MBB));
|
|
if (MBB == &UseMBB)
|
|
LiveIn.back().Kill = Use;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// This is essentially the same iterative algorithm that SSAUpdater uses,
|
|
// except we already have a dominator tree, so we don't have to recompute it.
|
|
void LiveRangeCalc::updateSSA() {
|
|
assert(Indexes && "Missing SlotIndexes");
|
|
assert(DomTree && "Missing dominator tree");
|
|
|
|
// Interate until convergence.
|
|
bool Changed;
|
|
do {
|
|
Changed = false;
|
|
// Propagate live-out values down the dominator tree, inserting phi-defs
|
|
// when necessary.
|
|
for (LiveInBlock &I : LiveIn) {
|
|
MachineDomTreeNode *Node = I.DomNode;
|
|
// Skip block if the live-in value has already been determined.
|
|
if (!Node)
|
|
continue;
|
|
MachineBasicBlock *MBB = Node->getBlock();
|
|
MachineDomTreeNode *IDom = Node->getIDom();
|
|
LiveOutPair IDomValue;
|
|
|
|
// We need a live-in value to a block with no immediate dominator?
|
|
// This is probably an unreachable block that has survived somehow.
|
|
bool needPHI = !IDom || !Seen.test(IDom->getBlock()->getNumber());
|
|
|
|
// IDom dominates all of our predecessors, but it may not be their
|
|
// immediate dominator. Check if any of them have live-out values that are
|
|
// properly dominated by IDom. If so, we need a phi-def here.
|
|
if (!needPHI) {
|
|
IDomValue = Map[IDom->getBlock()];
|
|
|
|
// Cache the DomTree node that defined the value.
|
|
if (IDomValue.first && IDomValue.first != &UndefVNI &&
|
|
!IDomValue.second) {
|
|
Map[IDom->getBlock()].second = IDomValue.second =
|
|
DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def));
|
|
}
|
|
|
|
for (MachineBasicBlock *Pred : MBB->predecessors()) {
|
|
LiveOutPair &Value = Map[Pred];
|
|
if (!Value.first || Value.first == IDomValue.first)
|
|
continue;
|
|
if (Value.first == &UndefVNI) {
|
|
needPHI = true;
|
|
break;
|
|
}
|
|
|
|
// Cache the DomTree node that defined the value.
|
|
if (!Value.second)
|
|
Value.second =
|
|
DomTree->getNode(Indexes->getMBBFromIndex(Value.first->def));
|
|
|
|
// This predecessor is carrying something other than IDomValue.
|
|
// It could be because IDomValue hasn't propagated yet, or it could be
|
|
// because MBB is in the dominance frontier of that value.
|
|
if (DomTree->dominates(IDom, Value.second)) {
|
|
needPHI = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// The value may be live-through even if Kill is set, as can happen when
|
|
// we are called from extendRange. In that case LiveOutSeen is true, and
|
|
// LiveOut indicates a foreign or missing value.
|
|
LiveOutPair &LOP = Map[MBB];
|
|
|
|
// Create a phi-def if required.
|
|
if (needPHI) {
|
|
Changed = true;
|
|
assert(Alloc && "Need VNInfo allocator to create PHI-defs");
|
|
SlotIndex Start, End;
|
|
std::tie(Start, End) = Indexes->getMBBRange(MBB);
|
|
LiveRange &LR = I.LR;
|
|
VNInfo *VNI = LR.getNextValue(Start, *Alloc);
|
|
I.Value = VNI;
|
|
// This block is done, we know the final value.
|
|
I.DomNode = nullptr;
|
|
|
|
// Add liveness since updateFromLiveIns now skips this node.
|
|
if (I.Kill.isValid()) {
|
|
if (VNI)
|
|
LR.addSegment(LiveInterval::Segment(Start, I.Kill, VNI));
|
|
} else {
|
|
if (VNI)
|
|
LR.addSegment(LiveInterval::Segment(Start, End, VNI));
|
|
LOP = LiveOutPair(VNI, Node);
|
|
}
|
|
} else if (IDomValue.first && IDomValue.first != &UndefVNI) {
|
|
// No phi-def here. Remember incoming value.
|
|
I.Value = IDomValue.first;
|
|
|
|
// If the IDomValue is killed in the block, don't propagate through.
|
|
if (I.Kill.isValid())
|
|
continue;
|
|
|
|
// Propagate IDomValue if it isn't killed:
|
|
// MBB is live-out and doesn't define its own value.
|
|
if (LOP.first == IDomValue.first)
|
|
continue;
|
|
Changed = true;
|
|
LOP = IDomValue;
|
|
}
|
|
}
|
|
} while (Changed);
|
|
}
|
|
|
|
bool LiveRangeCalc::isJointlyDominated(const MachineBasicBlock *MBB,
|
|
ArrayRef<SlotIndex> Defs,
|
|
const SlotIndexes &Indexes) {
|
|
const MachineFunction &MF = *MBB->getParent();
|
|
BitVector DefBlocks(MF.getNumBlockIDs());
|
|
for (SlotIndex I : Defs)
|
|
DefBlocks.set(Indexes.getMBBFromIndex(I)->getNumber());
|
|
|
|
SetVector<unsigned> PredQueue;
|
|
PredQueue.insert(MBB->getNumber());
|
|
for (unsigned i = 0; i != PredQueue.size(); ++i) {
|
|
unsigned BN = PredQueue[i];
|
|
if (DefBlocks[BN])
|
|
return true;
|
|
const MachineBasicBlock *B = MF.getBlockNumbered(BN);
|
|
for (const MachineBasicBlock *P : B->predecessors())
|
|
PredQueue.insert(P->getNumber());
|
|
}
|
|
return false;
|
|
}
|