| .. |
|
AsmParser
|
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
|
2020-07-24 16:41:03 +03:00 |
|
Disassembler
|
Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors"
|
2020-08-19 13:12:29 +05:30 |
|
MCTargetDesc
|
Reset PAL metadata when AMDGPU traget stream finishes
|
2020-08-17 10:56:11 -04:00 |
|
TargetInfo
|
CMake: Make most target symbols hidden by default
|
2020-01-14 19:46:52 -08:00 |
|
Utils
|
[AMDGPU] Remove unsound dependency on ISA version in waitcnt
|
2020-08-25 14:01:42 -07:00 |
|
AMDGPU.h
|
AMDGPU: Remove SIFixupVectorISel pass
|
2020-08-15 12:11:51 -04:00 |
|
AMDGPU.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
AMDGPUAliasAnalysis.cpp
|
[NFC] Remove unused GetUnderlyingObject paramenter
|
2020-07-31 02:10:03 -07:00 |
|
AMDGPUAliasAnalysis.h
|
Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
|
2020-06-25 16:00:44 +01:00 |
|
AMDGPUAlwaysInlinePass.cpp
|
AMDGPU: Hack out noinline on functions using LDS globals
|
2020-04-02 14:12:07 -04:00 |
|
AMDGPUAnnotateKernelFeatures.cpp
|
AMDGPU: Annotate functions that have stack objects
|
2020-05-19 18:51:00 -04:00 |
|
AMDGPUAnnotateUniformValues.cpp
|
AMDGPU: Put inexpensive ops first in AMDGPUAnnotateUniformValues::visitLoadInst
|
2020-07-30 14:37:06 -07:00 |
|
AMDGPUArgumentUsageInfo.cpp
|
AMDGPU/GlobalISel: Add types to special inputs
|
2020-07-06 17:00:55 -04:00 |
|
AMDGPUArgumentUsageInfo.h
|
AMDGPU: Use MCRegister for preloaded arguments
|
2020-07-20 13:34:28 -04:00 |
|
AMDGPUAsmPrinter.cpp
|
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
|
2020-07-02 17:20:15 +03:00 |
|
AMDGPUAsmPrinter.h
|
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
|
2020-02-13 22:08:55 -08:00 |
|
AMDGPUAtomicOptimizer.cpp
|
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
|
2020-05-29 17:54:17 -07:00 |
|
AMDGPUCallLowering.cpp
|
AMDGPU/GlobalISel: Stop using G_EXTRACT in argument lowering
|
2020-08-06 09:55:35 -04:00 |
|
AMDGPUCallLowering.h
|
AMDGPU/GlobalISel: Mark GlobalISel classes as final
|
2020-07-28 11:42:17 -04:00 |
|
AMDGPUCallingConv.td
|
[AMDGPU] Introduce more scratch registers in the ABI.
|
2020-05-05 23:02:58 +05:30 |
|
AMDGPUCodeGenPrepare.cpp
|
AMDGPU: Add flag to disable promotion of uniform i16 ops
|
2020-08-24 14:39:27 -04:00 |
|
AMDGPUCombine.td
|
AMDGPU/GlobalISel: Remove hack for combines forming illegal extloads
|
2020-08-19 14:15:38 -04:00 |
|
AMDGPUExportClustering.cpp
|
[AMDGPU] Strengthen export cluster ordering
|
2020-05-13 23:07:37 +09:00 |
|
AMDGPUExportClustering.h
|
[AMDGPU] Cluster shader exports
|
2020-05-07 19:05:38 +09:00 |
|
AMDGPUFeatures.td
|
AMDGPU: Change internal tracking of wave size
|
2020-06-01 17:55:08 -04:00 |
|
AMDGPUFixFunctionBitcasts.cpp
|
AMDGPU.h - reduce TargetMachine.h include. NFC.
|
2020-05-24 15:27:41 +01:00 |
|
AMDGPUFrameLowering.cpp
|
…
|
|
|
AMDGPUFrameLowering.h
|
[Alignment][NFC] Deprecate Align::None()
|
2020-01-24 12:53:58 +01:00 |
|
AMDGPUGISel.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
AMDGPUGenRegisterBankInfo.def
|
AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
|
2020-08-17 09:53:26 -04:00 |
|
AMDGPUGlobalISelUtils.cpp
|
AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
|
2020-02-21 13:35:40 -05:00 |
|
AMDGPUGlobalISelUtils.h
|
AMDGPU/GlobalISel: Start selecting image intrinsics
|
2020-03-30 17:33:04 -04:00 |
|
AMDGPUHSAMetadataStreamer.cpp
|
AMDGPU: Start interpreting byref on kernel arguments
|
2020-07-21 18:11:22 -04:00 |
|
AMDGPUHSAMetadataStreamer.h
|
AMDGPU: Start interpreting byref on kernel arguments
|
2020-07-21 18:11:22 -04:00 |
|
AMDGPUISelDAGToDAG.cpp
|
AMDGPU: Don't assert on misaligned DS read2/write2 offsets
|
2020-08-26 14:08:05 -04:00 |
|
AMDGPUISelLowering.cpp
|
[AMDGPU] Fix crash when dag-combining bitcast
|
2020-08-13 10:23:13 +08:00 |
|
AMDGPUISelLowering.h
|
AMDGPU: Remove ATOMIC_PK_FADD
|
2020-08-05 22:00:52 -04:00 |
|
AMDGPUInline.cpp
|
[NFC] Remove unused GetUnderlyingObject paramenter
|
2020-07-31 02:10:03 -07:00 |
|
AMDGPUInstCombineIntrinsic.cpp
|
[AMDGPU] Add A16/G16 to InstCombine
|
2020-08-20 10:51:49 +02:00 |
|
AMDGPUInstrInfo.cpp
|
[AMDGPU] Remove AMDGPURegisterInfo
|
2020-02-11 11:13:38 -08:00 |
|
AMDGPUInstrInfo.h
|
[AMDGPU] Add A16/G16 to InstCombine
|
2020-08-20 10:51:49 +02:00 |
|
AMDGPUInstrInfo.td
|
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
|
2020-06-16 21:06:25 -04:00 |
|
AMDGPUInstructionSelector.cpp
|
[AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size
|
2020-08-26 13:47:51 +01:00 |
|
AMDGPUInstructionSelector.h
|
[AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size
|
2020-08-26 13:47:51 +01:00 |
|
AMDGPUInstructions.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
AMDGPULegalizerInfo.cpp
|
AMDGPU/GlobalISel: Tolerate negated control flow intrinsic outputs
|
2020-08-26 08:58:54 -04:00 |
|
AMDGPULegalizerInfo.h
|
AMDGPU/GlobalISel: Prepare for more custom load lowerings
|
2020-08-11 11:09:05 -04:00 |
|
AMDGPULibCalls.cpp
|
Use llvm::is_contained where appropriate (NFC)
|
2020-07-27 10:20:44 -07:00 |
|
AMDGPULibFunc.cpp
|
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
|
2020-05-29 17:54:17 -07:00 |
|
AMDGPULibFunc.h
|
AMDGPULibFunc - fix include order. NFC.
|
2020-05-24 13:25:59 +01:00 |
|
AMDGPULowerIntrinsics.cpp
|
AMDGPU: Use caller subtarget, not intrinsic declaration
|
2020-08-27 16:42:09 -04:00 |
|
AMDGPULowerKernelArguments.cpp
|
AMDGPU: Start interpreting byref on kernel arguments
|
2020-07-21 18:11:22 -04:00 |
|
AMDGPULowerKernelAttributes.cpp
|
…
|
|
|
AMDGPUMCInstLower.cpp
|
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
|
2020-02-13 22:08:55 -08:00 |
|
AMDGPUMachineCFGStructurizer.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
AMDGPUMachineFunction.cpp
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
AMDGPUMachineFunction.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
AMDGPUMachineModuleInfo.cpp
|
…
|
|
|
AMDGPUMachineModuleInfo.h
|
…
|
|
|
AMDGPUMacroFusion.cpp
|
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
|
2020-03-11 17:59:21 +00:00 |
|
AMDGPUMacroFusion.h
|
…
|
|
|
AMDGPUOpenCLEnqueuedBlockLowering.cpp
|
Avoid SmallString.h include in MD5.h, NFC
|
2020-02-26 09:10:24 -08:00 |
|
AMDGPUPTNote.h
|
…
|
|
|
AMDGPUPerfHintAnalysis.cpp
|
AMDGPU.h - reduce TargetMachine.h include. NFC.
|
2020-05-24 15:27:41 +01:00 |
|
AMDGPUPerfHintAnalysis.h
|
…
|
|
|
AMDGPUPostLegalizerCombiner.cpp
|
AMDGPU/GlobalISel: Fix using post-legal combiner without LegalizerInfo
|
2020-08-17 09:19:22 -04:00 |
|
AMDGPUPreLegalizerCombiner.cpp
|
AMDGPU/GlobalISel: Mark GlobalISel classes as final
|
2020-07-28 11:42:17 -04:00 |
|
AMDGPUPrintfRuntimeBinding.cpp
|
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
|
2020-05-29 17:54:17 -07:00 |
|
AMDGPUPromoteAlloca.cpp
|
[NFC] Remove unused GetUnderlyingObject paramenter
|
2020-07-31 02:10:03 -07:00 |
|
AMDGPUPropagateAttributes.cpp
|
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
|
2020-03-26 14:43:44 -07:00 |
|
AMDGPURegBankCombiner.cpp
|
AMDGPU/GlobalISel: Mark GlobalISel classes as final
|
2020-07-28 11:42:17 -04:00 |
|
AMDGPURegisterBankInfo.cpp
|
AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
|
2020-08-24 17:54:34 -04:00 |
|
AMDGPURegisterBankInfo.h
|
AMDGPU/GlobalISel: Start trying to handle AGPR bank
|
2020-08-06 12:39:50 -04:00 |
|
AMDGPURegisterBanks.td
|
AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
|
2020-07-28 16:49:55 -04:00 |
|
AMDGPURewriteOutArguments.cpp
|
[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
|
2020-05-13 15:57:55 -07:00 |
|
AMDGPUSearchableTables.td
|
AMDGPU: Define raw/struct variants of buffer atomic fadd
|
2020-08-06 13:36:19 -04:00 |
|
AMDGPUSubtarget.cpp
|
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
|
2020-08-24 09:53:27 -04:00 |
|
AMDGPUSubtarget.h
|
AMDGPU/GlobalISel: Implement computeKnownBits for groupstaticsize
|
2020-08-27 19:39:44 -04:00 |
|
AMDGPUTargetMachine.cpp
|
AMDGPU: Remove SIFixupVectorISel pass
|
2020-08-15 12:11:51 -04:00 |
|
AMDGPUTargetMachine.h
|
Support addrspacecast initializers with isNoopAddrSpaceCast
|
2020-07-31 10:42:43 -04:00 |
|
AMDGPUTargetObjectFile.cpp
|
…
|
|
|
AMDGPUTargetObjectFile.h
|
AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
|
2020-05-24 13:57:02 +01:00 |
|
AMDGPUTargetTransformInfo.cpp
|
[AMDGPU][LoopUnroll] Increase BB size to analyze for complete unroll.
|
2020-08-20 10:41:47 +03:00 |
|
AMDGPUTargetTransformInfo.h
|
[AMDGPU] Reorganize GCN subtarget features for unaligned access
|
2020-08-21 12:26:31 +02:00 |
|
AMDGPUUnifyDivergentExitNodes.cpp
|
Reland "[NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init"
|
2020-07-16 13:40:01 +03:00 |
|
AMDGPUUnifyMetadata.cpp
|
Use llvm::is_contained where appropriate (NFC)
|
2020-07-27 10:20:44 -07:00 |
|
AMDILCFGStructurizer.cpp
|
…
|
|
|
AMDKernelCodeT.h
|
…
|
|
|
BUFInstructions.td
|
AMDGPU/GlobalISel: Select llvm.amdgcn.global.atomic.fadd
|
2020-08-12 10:04:53 -04:00 |
|
CMakeLists.txt
|
AMDGPU: Remove SIFixupVectorISel pass
|
2020-08-15 12:11:51 -04:00 |
|
CaymanInstructions.td
|
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
|
2020-07-08 19:14:49 +01:00 |
|
DSInstructions.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
EvergreenInstructions.td
|
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
|
2020-04-25 16:26:45 -07:00 |
|
FLATInstructions.td
|
AMDGPU: Match global saddr addressing mode
|
2020-08-17 15:28:14 -04:00 |
|
GCNDPPCombine.cpp
|
AMDGPU: Rename add/sub with carry out instructions
|
2020-07-16 13:16:30 -04:00 |
|
GCNHazardRecognizer.cpp
|
[AMDGPU] Fix MAI ld/st hazard handling
|
2020-08-14 17:07:37 -07:00 |
|
GCNHazardRecognizer.h
|
[AMDGPU] prefer non-mfma in post-RA schedule
|
2020-07-29 12:17:50 -07:00 |
|
GCNILPSched.cpp
|
…
|
|
|
GCNIterativeScheduler.cpp
|
[AMDGPU] Add file headers for few files where it is missing.
|
2020-01-31 02:06:41 +05:30 |
|
GCNIterativeScheduler.h
|
[AMDGPU] Add file headers for few files where it is missing.
|
2020-01-31 02:06:41 +05:30 |
|
GCNMinRegStrategy.cpp
|
SmallPtrSet::find -> SmallPtrSet::count
|
2020-06-07 22:38:08 +02:00 |
|
GCNNSAReassign.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNProcessors.td
|
[AMDGPU] gfx1031 target
|
2020-08-05 12:36:26 -07:00 |
|
GCNRegBankReassign.cpp
|
[AMDGPU] Avoid sorting stalls in regbank-reassign
|
2020-08-21 11:49:41 -07:00 |
|
GCNRegPressure.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNRegPressure.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNSchedStrategy.cpp
|
[AMDGPU] Fix not rescheduling without clustering
|
2020-08-07 11:15:58 -07:00 |
|
GCNSchedStrategy.h
|
[AMDGPU] Attempt to reschedule withou clustering
|
2020-01-27 10:27:16 -08:00 |
|
InstCombineTables.td
|
[InstCombine] Move target-specific inst combining
|
2020-07-22 15:59:49 +02:00 |
|
LLVMBuild.txt
|
…
|
|
|
MIMGInstructions.td
|
[AMDGPU] Add A16/G16 to InstCombine
|
2020-08-20 10:51:49 +02:00 |
|
R600.td
|
…
|
|
|
R600AsmPrinter.cpp
|
[MC] Add MCStreamer::emitInt{8,16,32,64}
|
2020-02-29 09:40:21 -08:00 |
|
R600AsmPrinter.h
|
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
|
2020-02-13 22:08:55 -08:00 |
|
R600ClauseMergePass.cpp
|
…
|
|
|
R600ControlFlowFinalizer.cpp
|
[AMDGPU] Make use of divideCeil. NFC.
|
2020-03-26 16:11:35 +00:00 |
|
R600Defines.h
|
…
|
|
|
R600EmitClauseMarkers.cpp
|
…
|
|
|
R600ExpandSpecialInstrs.cpp
|
[AMDGPU] Split R600 and GCN subregs
|
2020-02-10 08:29:56 -08:00 |
|
R600FrameLowering.cpp
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600FrameLowering.h
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600ISelLowering.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
R600ISelLowering.h
|
…
|
|
|
R600InstrFormats.td
|
…
|
|
|
R600InstrInfo.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600InstrInfo.h
|
…
|
|
|
R600Instructions.td
|
[NFC] Remove unused GetUnderlyingObject paramenter
|
2020-07-31 02:10:03 -07:00 |
|
R600MachineFunctionInfo.cpp
|
…
|
|
|
R600MachineFunctionInfo.h
|
…
|
|
|
R600MachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600MachineScheduler.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600OpenCLImageTypeLoweringPass.cpp
|
…
|
|
|
R600OptimizeVectorRegisters.cpp
|
AMDGPU: Use Register
|
2020-06-30 12:13:08 -04:00 |
|
R600Packetizer.cpp
|
…
|
|
|
R600Processors.td
|
…
|
|
|
R600RegisterInfo.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.td
|
[TBLGEN] Allow to override RC weight
|
2020-02-14 15:49:52 -08:00 |
|
R600Schedule.td
|
…
|
|
|
R700Instructions.td
|
…
|
|
|
SIAddIMGInit.cpp
|
[AMDGPU] Split R600 and GCN subregs
|
2020-02-10 08:29:56 -08:00 |
|
SIAnnotateControlFlow.cpp
|
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
|
2020-02-03 07:02:05 -08:00 |
|
SIDefines.h
|
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
|
2020-07-24 16:41:03 +03:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] Remove unused variable introduced in r251860
|
2020-08-27 13:28:32 +01:00 |
|
SIFixVGPRCopies.cpp
|
…
|
|
|
SIFoldOperands.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIFormMemoryClauses.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIFrameLowering.cpp
|
allSGPRSpillsAreDead() should use actual FP/BP frame indices
|
2020-08-20 16:15:53 -04:00 |
|
SIFrameLowering.h
|
AMDGPU: Correct prolog SP initialization logic
|
2020-08-05 15:47:53 -04:00 |
|
SIISelLowering.cpp
|
AMDGPU/GlobalISel: Implement computeKnownBits for groupstaticsize
|
2020-08-27 19:39:44 -04:00 |
|
SIISelLowering.h
|
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
|
2020-08-24 09:53:27 -04:00 |
|
SIInsertHardClauses.cpp
|
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
|
2020-06-01 22:52:34 +05:30 |
|
SIInsertSkips.cpp
|
[AMDGPU] Insert PS early exit at end of control flow
|
2020-07-03 14:04:34 +09:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Remove unsound dependency on ISA version in waitcnt
|
2020-08-25 14:01:42 -07:00 |
|
SIInstrFormats.td
|
AMDGPU: Start adding MODE register uses to instructions
|
2020-05-27 14:47:00 -04:00 |
|
SIInstrInfo.cpp
|
[AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK
|
2020-08-27 10:22:50 +02:00 |
|
SIInstrInfo.h
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SIInstrInfo.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
|
SIInstructions.td
|
[AMDGPU] Define spill opcodes for all AGPR sizes
|
2020-08-17 12:17:23 -07:00 |
|
SILoadStoreOptimizer.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SILowerControlFlow.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SILowerI1Copies.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SILowerSGPRSpills.cpp
|
[AMDGPU] Scavenge temp reg for AGPR spill
|
2020-08-05 13:29:19 -07:00 |
|
SIMachineFunctionInfo.cpp
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
SIMachineFunctionInfo.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
SIMachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIMachineScheduler.h
|
[AMDGPU] Use generated RegisterPressureSets enum
|
2020-02-18 10:34:03 -08:00 |
|
SIMemoryLegalizer.cpp
|
[AMDGPU] Make generating cache invalidating instructions optional
|
2020-07-27 09:24:11 +02:00 |
|
SIModeRegister.cpp
|
[AMDGPU] Avoid redundant mode register writes
|
2020-06-24 14:11:29 +01:00 |
|
SIOptimizeExecMasking.cpp
|
AMDGPU: Optimize copies to exec with other insts after exec def
|
2020-07-28 21:34:50 -04:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIPeepholeSDWA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIPostRABundler.cpp
|
AMDGPU: Do not bundle inline asm
|
2020-06-14 13:24:50 -04:00 |
|
SIPreAllocateWWMRegs.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIPreEmitPeephole.cpp
|
[AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
|
2020-08-13 21:52:41 +09:00 |
|
SIProgramInfo.h
|
…
|
|
|
SIRegisterInfo.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SIRegisterInfo.h
|
[NFC] Move getAll{S,V}GPR{32,128} methods to SIFrameLowering
|
2020-06-17 12:08:09 -04:00 |
|
SIRegisterInfo.td
|
AMDGPU: Define mode register
|
2020-05-23 13:24:42 -04:00 |
|
SIRemoveShortExecBranches.cpp
|
[AMDGPU] Don't remove short branches over kills
|
2020-02-03 09:26:52 +00:00 |
|
SISchedule.td
|
[AMDGPU] More accurate gfx10 latencies
|
2020-06-04 10:29:32 +01:00 |
|
SIShrinkInstructions.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIWholeQuadMode.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SMInstructions.td
|
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
|
2020-06-18 14:12:19 -04:00 |
|
SOPInstructions.td
|
AMDGPU/GlobalISel: Match andn2/orn2 for more types
|
2020-08-14 13:18:03 -04:00 |
|
VIInstrFormats.td
|
…
|
|
|
VOP1Instructions.td
|
[AMDGPU] Removed s_mov_regrd and mov_fed opcodes
|
2020-07-17 19:52:54 +03:00 |
|
VOP2Instructions.td
|
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
|
2020-07-28 11:18:05 -04:00 |
|
VOP3Instructions.td
|
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
|
2020-07-28 11:18:05 -04:00 |
|
VOP3PInstructions.td
|
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
|
2020-07-28 11:18:05 -04:00 |
|
VOPCInstructions.td
|
AMDGPU: Start adding MODE register uses to instructions
|
2020-05-27 14:47:00 -04:00 |
|
VOPInstructions.td
|
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
|
2020-07-28 11:18:05 -04:00 |
af1c1e20f4