Matt Arsenault 4bd7236193 AMDGPU: Fix handling of 16-bit immediates ... Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306		2016-12-10 00:39:12 +00:00
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expected-target-index-name.mir	MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it	2016-08-24 22:17:45 +00:00
fold-imm-f16-f32.mir	AMDGPU: Fix handling of 16-bit immediates	2016-12-10 00:39:12 +00:00
intrinsics.mir	GlobalISel: move type information to MachineRegisterInfo.	2016-09-09 11:46:34 +00:00
invalid-target-index-operand.mir	MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it	2016-08-24 22:17:45 +00:00
lit.local.cfg	…
target-index-operands.mir	AMDGPU: Add definitions for scalar store instructions	2016-10-28 21:55:15 +00:00