forked from OSchip/llvm-project
1691 lines
42 KiB
LLVM
1691 lines
42 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; The patterns for the 'W' suffixed RV64I instructions have the potential of
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; missing cases. This file checks all the variants of
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; sign-extended/zero-extended/any-extended inputs and outputs.
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; The 64-bit add instruction can safely be used when the result is anyext.
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define i32 @aext_addw_aext_aext(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_addw_aext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_addw_aext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_addw_aext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_addw_sext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_addw_sext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_addw_sext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_addw_zext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_addw_zext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_addw_zext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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; Always select addw when a signext result is required.
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define signext i32 @sext_addw_aext_aext(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: sext_addw_aext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sext_addw_aext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: sext_addw_aext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
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; RV64I-LABEL: sext_addw_sext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sext_addw_sext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: sext_addw_sext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
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; RV64I-LABEL: sext_addw_zext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sext_addw_zext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define signext i32 @sext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: sext_addw_zext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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; 64-bit add followed by zero-extension is a safe option when a zeroext result
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; is required.
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define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: zext_addw_aext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
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; RV64I-LABEL: zext_addw_aext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: zext_addw_aext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
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; RV64I-LABEL: zext_addw_sext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: zext_addw_sext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: zext_addw_sext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
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; RV64I-LABEL: zext_addw_zext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: zext_addw_zext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: zext_addw_zext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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ret i32 %1
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}
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; 64-bit sub is safe for an anyext result.
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define i32 @aext_subw_aext_aext(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_subw_aext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_subw_aext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_subw_aext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_subw_sext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_subw_sext_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_subw_sext_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
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; RV64I-LABEL: aext_subw_zext_aext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: aext_subw_zext_sext:
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|
; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
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; RV64I-LABEL: aext_subw_zext_zext:
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; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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|
%1 = sub i32 %a, %b
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ret i32 %1
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|
}
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|
; Always select subw for a signext result.
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define signext i32 @sext_subw_aext_aext(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: sext_subw_aext_aext:
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; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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|
; RV64I-NEXT: ret
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|
%1 = sub i32 %a, %b
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|
ret i32 %1
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|
}
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|
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define signext i32 @sext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sext_subw_aext_sext:
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|
; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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|
%1 = sub i32 %a, %b
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|
ret i32 %1
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|
}
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|
define signext i32 @sext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
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|
; RV64I-LABEL: sext_subw_aext_zext:
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|
; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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|
%1 = sub i32 %a, %b
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ret i32 %1
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|
}
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define signext i32 @sext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
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; RV64I-LABEL: sext_subw_sext_aext:
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|
; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i32 %a, %b
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ret i32 %1
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|
}
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define signext i32 @sext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_subw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
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|
%1 = sub i32 %a, %b
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|
ret i32 %1
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|
}
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|
define signext i32 @sext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_subw_sext_zext:
|
|
; RV64I: # %bb.0:
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|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
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ret i32 %1
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|
}
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|
|
define signext i32 @sext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_subw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_subw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_subw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: subw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
; 64-bit sub followed by zero-extension is safe for a zeroext result.
|
|
|
|
define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_subw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sub a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = sub i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
; 64-bit sll is a safe choice for an anyext result.
|
|
|
|
define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sllw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sllw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
; 64-bit sll followed by zero-extension for a zeroext result.
|
|
|
|
define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sllw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sllw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_srlw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_srlw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_srlw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srlw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: aext_sraw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: sext_sraw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_aext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_aext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_aext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_sext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_sext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_sext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_zext_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_zext_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
|
|
; RV64I-LABEL: zext_sraw_zext_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraw a0, a0, a1
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, %b
|
|
ret i32 %1
|
|
}
|
|
|
|
; addiw should be selected when there is a signext result.
|
|
|
|
define i32 @aext_addiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: aext_addiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 1
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_addiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: aext_addiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 2
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 2
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: aext_addiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 3
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 3
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_addiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: sext_addiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addiw a0, a0, 4
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 4
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_addiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: sext_addiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addiw a0, a0, 5
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 5
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: sext_addiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addiw a0, a0, 6
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 6
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: zext_addiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 7
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 7
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: zext_addiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 8
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 8
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: zext_addiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, a0, 9
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = add i32 %a, 9
|
|
ret i32 %1
|
|
}
|
|
|
|
; slliw should be selected whenever the return is signext.
|
|
|
|
define i32 @aext_slliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: aext_slliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 1
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_slliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: aext_slliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 2
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 2
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: aext_slliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 3
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 3
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_slliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: sext_slliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slliw a0, a0, 4
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 4
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_slliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: sext_slliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slliw a0, a0, 5
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 5
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: sext_slliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slliw a0, a0, 6
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 6
|
|
ret i32 %1
|
|
}
|
|
|
|
; TODO: the constant shifts could be combined.
|
|
|
|
define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: zext_slliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 7
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 7
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: zext_slliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 8
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 8
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: zext_slliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: slli a0, a0, 9
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = shl i32 %a, 9
|
|
ret i32 %1
|
|
}
|
|
|
|
; srliw should be selected unless the first operand is zeroext, when srli is
|
|
; equivalent.
|
|
|
|
define i32 @aext_srliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: aext_srliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 1
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: aext_srliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 2
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 2
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: aext_srliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srli a0, a0, 3
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 3
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: sext_srliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 4
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 4
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: sext_srliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 5
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 5
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: sext_srliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srli a0, a0, 6
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 6
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srliw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: zext_srliw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 7
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 7
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: zext_srliw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srliw a0, a0, 8
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 8
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: zext_srliw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srli a0, a0, 9
|
|
; RV64I-NEXT: ret
|
|
%1 = lshr i32 %a, 9
|
|
ret i32 %1
|
|
}
|
|
|
|
; srai is equivalent to sraiw if the first operand is sign-extended.
|
|
|
|
define i32 @aext_sraiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: aext_sraiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraiw a0, a0, 1
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 1
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: aext_sraiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srai a0, a0, 2
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 2
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @aext_sraiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: aext_sraiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraiw a0, a0, 3
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 3
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: sext_sraiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraiw a0, a0, 4
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 4
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: sext_sraiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srai a0, a0, 5
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 5
|
|
ret i32 %1
|
|
}
|
|
|
|
define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: sext_sraiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sraiw a0, a0, 6
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 6
|
|
ret i32 %1
|
|
}
|
|
|
|
; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
|
|
; the srli could be merged in to the shifts used for zero-extension.
|
|
|
|
define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
|
|
; RV64I-LABEL: zext_sraiw_aext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sext.w a0, a0
|
|
; RV64I-NEXT: srli a0, a0, 7
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 7
|
|
ret i32 %1
|
|
}
|
|
|
|
define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
|
|
; RV64I-LABEL: zext_sraiw_sext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: srli a0, a0, 8
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 8
|
|
ret i32 %1
|
|
}
|
|
|
|
; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
|
|
; the srli could be merged in to the shifts used for zero-extension.
|
|
|
|
define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
|
|
; RV64I-LABEL: zext_sraiw_zext:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: sext.w a0, a0
|
|
; RV64I-NEXT: srli a0, a0, 9
|
|
; RV64I-NEXT: slli a0, a0, 32
|
|
; RV64I-NEXT: srli a0, a0, 32
|
|
; RV64I-NEXT: ret
|
|
%1 = ashr i32 %a, 9
|
|
ret i32 %1
|
|
}
|