forked from OSchip/llvm-project
1078 lines
43 KiB
C++
1078 lines
43 KiB
C++
//===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
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#define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
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#include "StatepointLowering.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallSite.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Statepoint.h"
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#include "llvm/Support/BranchProbability.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MachineValueType.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <utility>
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#include <vector>
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namespace llvm {
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class AllocaInst;
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class AtomicCmpXchgInst;
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class AtomicRMWInst;
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class BasicBlock;
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class BranchInst;
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class CallInst;
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class CatchPadInst;
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class CatchReturnInst;
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class CatchSwitchInst;
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class CleanupPadInst;
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class CleanupReturnInst;
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class Constant;
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class ConstantInt;
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class ConstrainedFPIntrinsic;
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class DbgValueInst;
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class DataLayout;
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class DIExpression;
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class DILocalVariable;
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class DILocation;
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class FenceInst;
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class FunctionLoweringInfo;
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class GCFunctionInfo;
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class GCRelocateInst;
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class GCResultInst;
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class IndirectBrInst;
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class InvokeInst;
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class LandingPadInst;
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class LLVMContext;
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class LoadInst;
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class MachineBasicBlock;
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class PHINode;
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class ResumeInst;
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class ReturnInst;
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class SDDbgValue;
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class StoreInst;
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class SwitchInst;
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class TargetLibraryInfo;
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class TargetMachine;
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class Type;
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class VAArgInst;
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class UnreachableInst;
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class Use;
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class User;
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class Value;
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//===----------------------------------------------------------------------===//
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/// SelectionDAGBuilder - This is the common target-independent lowering
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/// implementation that is parameterized by a TargetLowering object.
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///
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class SelectionDAGBuilder {
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/// CurInst - The current instruction being visited
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const Instruction *CurInst = nullptr;
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DenseMap<const Value*, SDValue> NodeMap;
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/// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
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/// to preserve debug information for incoming arguments.
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DenseMap<const Value*, SDValue> UnusedArgNodeMap;
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/// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
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class DanglingDebugInfo {
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const DbgValueInst* DI = nullptr;
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DebugLoc dl;
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unsigned SDNodeOrder = 0;
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public:
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DanglingDebugInfo() = default;
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DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO)
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: DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {}
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const DbgValueInst* getDI() { return DI; }
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DebugLoc getdl() { return dl; }
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unsigned getSDNodeOrder() { return SDNodeOrder; }
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};
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/// DanglingDebugInfoVector - Helper type for DanglingDebugInfoMap.
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typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector;
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/// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
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/// yet seen the referent. We defer handling these until we do see it.
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DenseMap<const Value*, DanglingDebugInfoVector> DanglingDebugInfoMap;
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public:
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/// PendingLoads - Loads are not emitted to the program immediately. We bunch
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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SmallVector<SDValue, 8> PendingLoads;
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/// State used while lowering a statepoint sequence (gc_statepoint,
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/// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
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StatepointLoweringState StatepointLowering;
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private:
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// instruction, but they have no other ordering requirements. We bunch them
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/// up and the emit a single tokenfactor for them just before terminator
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/// instructions.
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SmallVector<SDValue, 8> PendingExports;
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/// SDNodeOrder - A unique monotonically increasing number used to order the
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/// SDNodes we create.
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unsigned SDNodeOrder;
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enum CaseClusterKind {
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/// A cluster of adjacent case labels with the same destination, or just one
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/// case.
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CC_Range,
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/// A cluster of cases suitable for jump table lowering.
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CC_JumpTable,
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/// A cluster of cases suitable for bit test lowering.
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CC_BitTests
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};
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/// A cluster of case labels.
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struct CaseCluster {
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CaseClusterKind Kind;
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const ConstantInt *Low, *High;
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union {
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MachineBasicBlock *MBB;
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unsigned JTCasesIndex;
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unsigned BTCasesIndex;
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};
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BranchProbability Prob;
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static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
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MachineBasicBlock *MBB, BranchProbability Prob) {
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CaseCluster C;
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C.Kind = CC_Range;
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C.Low = Low;
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C.High = High;
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C.MBB = MBB;
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C.Prob = Prob;
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return C;
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}
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static CaseCluster jumpTable(const ConstantInt *Low,
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const ConstantInt *High, unsigned JTCasesIndex,
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BranchProbability Prob) {
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CaseCluster C;
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C.Kind = CC_JumpTable;
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C.Low = Low;
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C.High = High;
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C.JTCasesIndex = JTCasesIndex;
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C.Prob = Prob;
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return C;
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}
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static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
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unsigned BTCasesIndex, BranchProbability Prob) {
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CaseCluster C;
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C.Kind = CC_BitTests;
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C.Low = Low;
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C.High = High;
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C.BTCasesIndex = BTCasesIndex;
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C.Prob = Prob;
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return C;
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}
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};
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using CaseClusterVector = std::vector<CaseCluster>;
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using CaseClusterIt = CaseClusterVector::iterator;
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struct CaseBits {
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uint64_t Mask = 0;
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MachineBasicBlock* BB = nullptr;
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unsigned Bits = 0;
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BranchProbability ExtraProb;
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CaseBits() = default;
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CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
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BranchProbability Prob):
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Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) {}
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};
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using CaseBitsVector = std::vector<CaseBits>;
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/// Sort Clusters and merge adjacent cases.
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void sortAndRangeify(CaseClusterVector &Clusters);
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/// CaseBlock - This structure is used to communicate between
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/// SelectionDAGBuilder and SDISel for the code generation of additional basic
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/// blocks needed by multi-case switch statements.
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struct CaseBlock {
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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const Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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/// The debug location of the instruction this CaseBlock was
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/// produced from.
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SDLoc DL;
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// TrueProb/FalseProb - branch weights.
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BranchProbability TrueProb, FalseProb;
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CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
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const Value *cmpmiddle, MachineBasicBlock *truebb,
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MachineBasicBlock *falsebb, MachineBasicBlock *me,
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SDLoc dl,
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BranchProbability trueprob = BranchProbability::getUnknown(),
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BranchProbability falseprob = BranchProbability::getUnknown())
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me), DL(dl),
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TrueProb(trueprob), FalseProb(falseprob) {}
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};
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struct JumpTable {
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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};
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struct JumpTableHeader {
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APInt First;
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APInt Last;
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const Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
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bool E = false)
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: First(std::move(F)), Last(std::move(L)), SValue(SV), HeaderBB(H),
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Emitted(E) {}
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};
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using JumpTableBlock = std::pair<JumpTableHeader, JumpTable>;
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struct BitTestCase {
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uint64_t Mask;
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MachineBasicBlock *ThisBB;
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MachineBasicBlock *TargetBB;
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BranchProbability ExtraProb;
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
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BranchProbability Prob):
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Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) {}
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};
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using BitTestInfo = SmallVector<BitTestCase, 3>;
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struct BitTestBlock {
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APInt First;
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APInt Range;
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const Value *SValue;
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unsigned Reg;
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MVT RegVT;
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bool Emitted;
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bool ContiguousRange;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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BranchProbability Prob;
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BranchProbability DefaultProb;
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BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT,
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bool E, bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
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BitTestInfo C, BranchProbability Pr)
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: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
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RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
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Cases(std::move(C)), Prob(Pr) {}
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};
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/// Return the range of value in [First..Last].
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uint64_t getJumpTableRange(const CaseClusterVector &Clusters, unsigned First,
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unsigned Last) const;
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/// Return the number of cases in [First..Last].
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uint64_t getJumpTableNumCases(const SmallVectorImpl<unsigned> &TotalCases,
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unsigned First, unsigned Last) const;
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/// Build a jump table cluster from Clusters[First..Last]. Returns false if it
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/// decides it's not a good idea.
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bool buildJumpTable(const CaseClusterVector &Clusters, unsigned First,
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unsigned Last, const SwitchInst *SI,
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MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
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/// Find clusters of cases suitable for jump table lowering.
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void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
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MachineBasicBlock *DefaultMBB);
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/// Build a bit test cluster from Clusters[First..Last]. Returns false if it
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/// decides it's not a good idea.
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bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
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const SwitchInst *SI, CaseCluster &BTCluster);
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/// Find clusters of cases suitable for bit test lowering.
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void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
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struct SwitchWorkListItem {
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MachineBasicBlock *MBB;
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CaseClusterIt FirstCluster;
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CaseClusterIt LastCluster;
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const ConstantInt *GE;
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const ConstantInt *LT;
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BranchProbability DefaultProb;
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};
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using SwitchWorkList = SmallVector<SwitchWorkListItem, 4>;
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/// Determine the rank by weight of CC in [First,Last]. If CC has more weight
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/// than each cluster in the range, its rank is 0.
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static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
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CaseClusterIt Last);
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/// Emit comparison and split W into two subtrees.
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void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
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Value *Cond, MachineBasicBlock *SwitchMBB);
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/// Lower W.
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void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
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MachineBasicBlock *SwitchMBB,
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MachineBasicBlock *DefaultMBB);
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/// Peel the top probability case if it exceeds the threshold
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MachineBasicBlock *peelDominantCaseCluster(const SwitchInst &SI,
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CaseClusterVector &Clusters,
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BranchProbability &PeeledCaseProb);
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/// A class which encapsulates all of the information needed to generate a
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/// stack protector check and signals to isel via its state being initialized
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/// that a stack protector needs to be generated.
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///
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/// *NOTE* The following is a high level documentation of SelectionDAG Stack
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/// Protector Generation. The reason that it is placed here is for a lack of
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/// other good places to stick it.
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///
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/// High Level Overview of SelectionDAG Stack Protector Generation:
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///
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/// Previously, generation of stack protectors was done exclusively in the
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/// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
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/// splitting basic blocks at the IR level to create the success/failure basic
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/// blocks in the tail of the basic block in question. As a result of this,
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/// calls that would have qualified for the sibling call optimization were no
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/// longer eligible for optimization since said calls were no longer right in
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/// the "tail position" (i.e. the immediate predecessor of a ReturnInst
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/// instruction).
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///
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/// Then it was noticed that since the sibling call optimization causes the
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/// callee to reuse the caller's stack, if we could delay the generation of
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/// the stack protector check until later in CodeGen after the sibling call
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/// decision was made, we get both the tail call optimization and the stack
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/// protector check!
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///
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/// A few goals in solving this problem were:
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///
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/// 1. Preserve the architecture independence of stack protector generation.
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///
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/// 2. Preserve the normal IR level stack protector check for platforms like
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/// OpenBSD for which we support platform-specific stack protector
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/// generation.
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///
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/// The main problem that guided the present solution is that one can not
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/// solve this problem in an architecture independent manner at the IR level
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/// only. This is because:
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///
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/// 1. The decision on whether or not to perform a sibling call on certain
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/// platforms (for instance i386) requires lower level information
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/// related to available registers that can not be known at the IR level.
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///
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/// 2. Even if the previous point were not true, the decision on whether to
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/// perform a tail call is done in LowerCallTo in SelectionDAG which
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/// occurs after the Stack Protector Pass. As a result, one would need to
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/// put the relevant callinst into the stack protector check success
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/// basic block (where the return inst is placed) and then move it back
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/// later at SelectionDAG/MI time before the stack protector check if the
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/// tail call optimization failed. The MI level option was nixed
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/// immediately since it would require platform-specific pattern
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/// matching. The SelectionDAG level option was nixed because
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/// SelectionDAG only processes one IR level basic block at a time
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/// implying one could not create a DAG Combine to move the callinst.
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///
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/// To get around this problem a few things were realized:
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///
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/// 1. While one can not handle multiple IR level basic blocks at the
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/// SelectionDAG Level, one can generate multiple machine basic blocks
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/// for one IR level basic block. This is how we handle bit tests and
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/// switches.
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///
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/// 2. At the MI level, tail calls are represented via a special return
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/// MIInst called "tcreturn". Thus if we know the basic block in which we
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/// wish to insert the stack protector check, we get the correct behavior
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/// by always inserting the stack protector check right before the return
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/// statement. This is a "magical transformation" since no matter where
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/// the stack protector check intrinsic is, we always insert the stack
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/// protector check code at the end of the BB.
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///
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/// Given the aforementioned constraints, the following solution was devised:
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///
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/// 1. On platforms that do not support SelectionDAG stack protector check
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/// generation, allow for the normal IR level stack protector check
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/// generation to continue.
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///
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/// 2. On platforms that do support SelectionDAG stack protector check
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/// generation:
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///
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/// a. Use the IR level stack protector pass to decide if a stack
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/// protector is required/which BB we insert the stack protector check
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/// in by reusing the logic already therein. If we wish to generate a
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/// stack protector check in a basic block, we place a special IR
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/// intrinsic called llvm.stackprotectorcheck right before the BB's
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/// returninst or if there is a callinst that could potentially be
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/// sibling call optimized, before the call inst.
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///
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/// b. Then when a BB with said intrinsic is processed, we codegen the BB
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/// normally via SelectBasicBlock. In said process, when we visit the
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/// stack protector check, we do not actually emit anything into the
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/// BB. Instead, we just initialize the stack protector descriptor
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/// class (which involves stashing information/creating the success
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/// mbbb and the failure mbb if we have not created one for this
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/// function yet) and export the guard variable that we are going to
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/// compare.
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///
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/// c. After we finish selecting the basic block, in FinishBasicBlock if
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/// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
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/// initialized, we produce the validation code with one of these
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/// techniques:
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/// 1) with a call to a guard check function
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/// 2) with inlined instrumentation
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///
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/// 1) We insert a call to the check function before the terminator.
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///
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/// 2) We first find a splice point in the parent basic block
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/// before the terminator and then splice the terminator of said basic
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/// block into the success basic block. Then we code-gen a new tail for
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/// the parent basic block consisting of the two loads, the comparison,
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/// and finally two branches to the success/failure basic blocks. We
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/// conclude by code-gening the failure basic block if we have not
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/// code-gened it already (all stack protector checks we generate in
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/// the same function, use the same failure basic block).
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|
class StackProtectorDescriptor {
|
|
public:
|
|
StackProtectorDescriptor() = default;
|
|
|
|
/// Returns true if all fields of the stack protector descriptor are
|
|
/// initialized implying that we should/are ready to emit a stack protector.
|
|
bool shouldEmitStackProtector() const {
|
|
return ParentMBB && SuccessMBB && FailureMBB;
|
|
}
|
|
|
|
bool shouldEmitFunctionBasedCheckStackProtector() const {
|
|
return ParentMBB && !SuccessMBB && !FailureMBB;
|
|
}
|
|
|
|
/// Initialize the stack protector descriptor structure for a new basic
|
|
/// block.
|
|
void initialize(const BasicBlock *BB, MachineBasicBlock *MBB,
|
|
bool FunctionBasedInstrumentation) {
|
|
// Make sure we are not initialized yet.
|
|
assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
|
|
"already initialized!");
|
|
ParentMBB = MBB;
|
|
if (!FunctionBasedInstrumentation) {
|
|
SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
|
|
FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
|
|
}
|
|
}
|
|
|
|
/// Reset state that changes when we handle different basic blocks.
|
|
///
|
|
/// This currently includes:
|
|
///
|
|
/// 1. The specific basic block we are generating a
|
|
/// stack protector for (ParentMBB).
|
|
///
|
|
/// 2. The successor machine basic block that will contain the tail of
|
|
/// parent mbb after we create the stack protector check (SuccessMBB). This
|
|
/// BB is visited only on stack protector check success.
|
|
void resetPerBBState() {
|
|
ParentMBB = nullptr;
|
|
SuccessMBB = nullptr;
|
|
}
|
|
|
|
/// Reset state that only changes when we switch functions.
|
|
///
|
|
/// This currently includes:
|
|
///
|
|
/// 1. FailureMBB since we reuse the failure code path for all stack
|
|
/// protector checks created in an individual function.
|
|
///
|
|
/// 2.The guard variable since the guard variable we are checking against is
|
|
/// always the same.
|
|
void resetPerFunctionState() {
|
|
FailureMBB = nullptr;
|
|
}
|
|
|
|
MachineBasicBlock *getParentMBB() { return ParentMBB; }
|
|
MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
|
|
MachineBasicBlock *getFailureMBB() { return FailureMBB; }
|
|
|
|
private:
|
|
/// The basic block for which we are generating the stack protector.
|
|
///
|
|
/// As a result of stack protector generation, we will splice the
|
|
/// terminators of this basic block into the successor mbb SuccessMBB and
|
|
/// replace it with a compare/branch to the successor mbbs
|
|
/// SuccessMBB/FailureMBB depending on whether or not the stack protector
|
|
/// was violated.
|
|
MachineBasicBlock *ParentMBB = nullptr;
|
|
|
|
/// A basic block visited on stack protector check success that contains the
|
|
/// terminators of ParentMBB.
|
|
MachineBasicBlock *SuccessMBB = nullptr;
|
|
|
|
/// This basic block visited on stack protector check failure that will
|
|
/// contain a call to __stack_chk_fail().
|
|
MachineBasicBlock *FailureMBB = nullptr;
|
|
|
|
/// Add a successor machine basic block to ParentMBB. If the successor mbb
|
|
/// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
|
|
/// block will be created. Assign a large weight if IsLikely is true.
|
|
MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
|
|
MachineBasicBlock *ParentMBB,
|
|
bool IsLikely,
|
|
MachineBasicBlock *SuccMBB = nullptr);
|
|
};
|
|
|
|
private:
|
|
const TargetMachine &TM;
|
|
|
|
public:
|
|
/// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
|
|
/// nodes without a corresponding SDNode.
|
|
static const unsigned LowestSDNodeOrder = 1;
|
|
|
|
SelectionDAG &DAG;
|
|
const DataLayout *DL = nullptr;
|
|
AliasAnalysis *AA = nullptr;
|
|
const TargetLibraryInfo *LibInfo;
|
|
|
|
/// SwitchCases - Vector of CaseBlock structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<CaseBlock> SwitchCases;
|
|
|
|
/// JTCases - Vector of JumpTable structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<JumpTableBlock> JTCases;
|
|
|
|
/// BitTestCases - Vector of BitTestBlock structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<BitTestBlock> BitTestCases;
|
|
|
|
/// A StackProtectorDescriptor structure used to communicate stack protector
|
|
/// information in between SelectBasicBlock and FinishBasicBlock.
|
|
StackProtectorDescriptor SPDescriptor;
|
|
|
|
// Emit PHI-node-operand constants only once even if used by multiple
|
|
// PHI nodes.
|
|
DenseMap<const Constant *, unsigned> ConstantsOut;
|
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
///
|
|
FunctionLoweringInfo &FuncInfo;
|
|
|
|
/// GFI - Garbage collection metadata for the function.
|
|
GCFunctionInfo *GFI;
|
|
|
|
/// LPadToCallSiteMap - Map a landing pad to the call site indexes.
|
|
DenseMap<MachineBasicBlock *, SmallVector<unsigned, 4>> LPadToCallSiteMap;
|
|
|
|
/// HasTailCall - This is set to true if a call in the current
|
|
/// block has been translated as a tail call. In this case,
|
|
/// no subsequent DAG nodes should be created.
|
|
bool HasTailCall = false;
|
|
|
|
LLVMContext *Context;
|
|
|
|
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
|
|
CodeGenOpt::Level ol)
|
|
: SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
|
|
FuncInfo(funcinfo) {}
|
|
|
|
void init(GCFunctionInfo *gfi, AliasAnalysis *AA,
|
|
const TargetLibraryInfo *li);
|
|
|
|
/// Clear out the current SelectionDAG and the associated state and prepare
|
|
/// this SelectionDAGBuilder object to be used for a new block. This doesn't
|
|
/// clear out information about additional blocks that are needed to complete
|
|
/// switch lowering or PHI node updating; that information is cleared out as
|
|
/// it is consumed.
|
|
void clear();
|
|
|
|
/// Clear the dangling debug information map. This function is separated from
|
|
/// the clear so that debug information that is dangling in a basic block can
|
|
/// be properly resolved in a different basic block. This allows the
|
|
/// SelectionDAG to resolve dangling debug information attached to PHI nodes.
|
|
void clearDanglingDebugInfo();
|
|
|
|
/// Return the current virtual root of the Selection DAG, flushing any
|
|
/// PendingLoad items. This must be done before emitting a store or any other
|
|
/// node that may need to be ordered after any prior load instructions.
|
|
SDValue getRoot();
|
|
|
|
/// Similar to getRoot, but instead of flushing all the PendingLoad items,
|
|
/// flush all the PendingExports items. It is necessary to do this before
|
|
/// emitting a terminator instruction.
|
|
SDValue getControlRoot();
|
|
|
|
SDLoc getCurSDLoc() const {
|
|
return SDLoc(CurInst, SDNodeOrder);
|
|
}
|
|
|
|
DebugLoc getCurDebugLoc() const {
|
|
return CurInst ? CurInst->getDebugLoc() : DebugLoc();
|
|
}
|
|
|
|
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
|
|
|
|
void visit(const Instruction &I);
|
|
|
|
void visit(unsigned Opcode, const User &I);
|
|
|
|
/// getCopyFromRegs - If there was virtual register allocated for the value V
|
|
/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
|
|
SDValue getCopyFromRegs(const Value *V, Type *Ty);
|
|
|
|
/// If we have dangling debug info that describes \p Variable, or an
|
|
/// overlapping part of variable considering the \p Expr, then this method
|
|
/// weill drop that debug info as it isn't valid any longer.
|
|
void dropDanglingDebugInfo(const DILocalVariable *Variable,
|
|
const DIExpression *Expr);
|
|
|
|
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
|
|
// generate the debug data structures now that we've seen its definition.
|
|
void resolveDanglingDebugInfo(const Value *V, SDValue Val);
|
|
|
|
SDValue getValue(const Value *V);
|
|
bool findValue(const Value *V) const;
|
|
|
|
/// Return the SDNode for the specified IR value if it exists.
|
|
SDNode *getNodeForIRValue(const Value *V) {
|
|
if (NodeMap.find(V) == NodeMap.end())
|
|
return nullptr;
|
|
return NodeMap[V].getNode();
|
|
}
|
|
|
|
SDValue getNonRegisterValue(const Value *V);
|
|
SDValue getValueImpl(const Value *V);
|
|
|
|
void setValue(const Value *V, SDValue NewN) {
|
|
SDValue &N = NodeMap[V];
|
|
assert(!N.getNode() && "Already set a value for this node!");
|
|
N = NewN;
|
|
}
|
|
|
|
void setUnusedArgValue(const Value *V, SDValue NewN) {
|
|
SDValue &N = UnusedArgNodeMap[V];
|
|
assert(!N.getNode() && "Already set a value for this node!");
|
|
N = NewN;
|
|
}
|
|
|
|
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
|
MachineBasicBlock *SwitchBB,
|
|
Instruction::BinaryOps Opc, BranchProbability TProb,
|
|
BranchProbability FProb, bool InvertCond);
|
|
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
MachineBasicBlock *CurBB,
|
|
MachineBasicBlock *SwitchBB,
|
|
BranchProbability TProb, BranchProbability FProb,
|
|
bool InvertCond);
|
|
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
|
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
|
void CopyToExportRegsIfNeeded(const Value *V);
|
|
void ExportFromCurrentBlock(const Value *V);
|
|
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
|
|
const BasicBlock *EHPadBB = nullptr);
|
|
|
|
// Lower range metadata from 0 to N to assert zext to an integer of nearest
|
|
// floor power of two.
|
|
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I,
|
|
SDValue Op);
|
|
|
|
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI,
|
|
ImmutableCallSite CS, unsigned ArgIdx,
|
|
unsigned NumArgs, SDValue Callee,
|
|
Type *ReturnTy, bool IsPatchPoint);
|
|
|
|
std::pair<SDValue, SDValue>
|
|
lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
|
|
const BasicBlock *EHPadBB = nullptr);
|
|
|
|
/// UpdateSplitBlock - When an MBB was split during scheduling, update the
|
|
/// references that need to refer to the last resulting block.
|
|
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
|
|
|
|
/// Describes a gc.statepoint or a gc.statepoint like thing for the purposes
|
|
/// of lowering into a STATEPOINT node.
|
|
struct StatepointLoweringInfo {
|
|
/// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set
|
|
/// of gc pointers this STATEPOINT has to relocate.
|
|
SmallVector<const Value *, 16> Bases;
|
|
SmallVector<const Value *, 16> Ptrs;
|
|
|
|
/// The set of gc.relocate calls associated with this gc.statepoint.
|
|
SmallVector<const GCRelocateInst *, 16> GCRelocates;
|
|
|
|
/// The full list of gc arguments to the gc.statepoint being lowered.
|
|
ArrayRef<const Use> GCArgs;
|
|
|
|
/// The gc.statepoint instruction.
|
|
const Instruction *StatepointInstr = nullptr;
|
|
|
|
/// The list of gc transition arguments present in the gc.statepoint being
|
|
/// lowered.
|
|
ArrayRef<const Use> GCTransitionArgs;
|
|
|
|
/// The ID that the resulting STATEPOINT instruction has to report.
|
|
unsigned ID = -1;
|
|
|
|
/// Information regarding the underlying call instruction.
|
|
TargetLowering::CallLoweringInfo CLI;
|
|
|
|
/// The deoptimization state associated with this gc.statepoint call, if
|
|
/// any.
|
|
ArrayRef<const Use> DeoptState;
|
|
|
|
/// Flags associated with the meta arguments being lowered.
|
|
uint64_t StatepointFlags = -1;
|
|
|
|
/// The number of patchable bytes the call needs to get lowered into.
|
|
unsigned NumPatchBytes = -1;
|
|
|
|
/// The exception handling unwind destination, in case this represents an
|
|
/// invoke of gc.statepoint.
|
|
const BasicBlock *EHPadBB = nullptr;
|
|
|
|
explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {}
|
|
};
|
|
|
|
/// Lower \p SLI into a STATEPOINT instruction.
|
|
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI);
|
|
|
|
// This function is responsible for the whole statepoint lowering process.
|
|
// It uniformly handles invoke and call statepoints.
|
|
void LowerStatepoint(ImmutableStatepoint ISP,
|
|
const BasicBlock *EHPadBB = nullptr);
|
|
|
|
void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee,
|
|
const BasicBlock *EHPadBB);
|
|
|
|
void LowerDeoptimizeCall(const CallInst *CI);
|
|
void LowerDeoptimizingReturn();
|
|
|
|
void LowerCallSiteWithDeoptBundleImpl(ImmutableCallSite CS, SDValue Callee,
|
|
const BasicBlock *EHPadBB,
|
|
bool VarArgDisallowed,
|
|
bool ForceVoidReturnTy);
|
|
|
|
/// Returns the type of FrameIndex and TargetFrameIndex nodes.
|
|
MVT getFrameIndexTy() {
|
|
return DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout());
|
|
}
|
|
|
|
private:
|
|
// Terminator instructions.
|
|
void visitRet(const ReturnInst &I);
|
|
void visitBr(const BranchInst &I);
|
|
void visitSwitch(const SwitchInst &I);
|
|
void visitIndirectBr(const IndirectBrInst &I);
|
|
void visitUnreachable(const UnreachableInst &I);
|
|
void visitCleanupRet(const CleanupReturnInst &I);
|
|
void visitCatchSwitch(const CatchSwitchInst &I);
|
|
void visitCatchRet(const CatchReturnInst &I);
|
|
void visitCatchPad(const CatchPadInst &I);
|
|
void visitCleanupPad(const CleanupPadInst &CPI);
|
|
|
|
BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
|
|
const MachineBasicBlock *Dst) const;
|
|
void addSuccessorWithProb(
|
|
MachineBasicBlock *Src, MachineBasicBlock *Dst,
|
|
BranchProbability Prob = BranchProbability::getUnknown());
|
|
|
|
public:
|
|
void visitSwitchCase(CaseBlock &CB,
|
|
MachineBasicBlock *SwitchBB);
|
|
void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
|
|
MachineBasicBlock *ParentBB);
|
|
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
|
|
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
|
|
void visitBitTestCase(BitTestBlock &BB,
|
|
MachineBasicBlock* NextMBB,
|
|
BranchProbability BranchProbToNext,
|
|
unsigned Reg,
|
|
BitTestCase &B,
|
|
MachineBasicBlock *SwitchBB);
|
|
void visitJumpTable(JumpTable &JT);
|
|
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
|
|
MachineBasicBlock *SwitchBB);
|
|
|
|
private:
|
|
// These all get lowered before this pass.
|
|
void visitInvoke(const InvokeInst &I);
|
|
void visitResume(const ResumeInst &I);
|
|
|
|
void visitUnary(const User &I, unsigned Opcode);
|
|
void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
|
|
|
|
void visitBinary(const User &I, unsigned Opcode);
|
|
void visitShift(const User &I, unsigned Opcode);
|
|
void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
|
|
void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
|
|
void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
|
|
void visitFSub(const User &I);
|
|
void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
|
|
void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
|
|
void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
|
|
void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
|
|
void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
|
|
void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
|
|
void visitSDiv(const User &I);
|
|
void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
|
|
void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
|
|
void visitOr (const User &I) { visitBinary(I, ISD::OR); }
|
|
void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
|
|
void visitShl (const User &I) { visitShift(I, ISD::SHL); }
|
|
void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
|
void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
|
void visitICmp(const User &I);
|
|
void visitFCmp(const User &I);
|
|
// Visit the conversion instructions
|
|
void visitTrunc(const User &I);
|
|
void visitZExt(const User &I);
|
|
void visitSExt(const User &I);
|
|
void visitFPTrunc(const User &I);
|
|
void visitFPExt(const User &I);
|
|
void visitFPToUI(const User &I);
|
|
void visitFPToSI(const User &I);
|
|
void visitUIToFP(const User &I);
|
|
void visitSIToFP(const User &I);
|
|
void visitPtrToInt(const User &I);
|
|
void visitIntToPtr(const User &I);
|
|
void visitBitCast(const User &I);
|
|
void visitAddrSpaceCast(const User &I);
|
|
|
|
void visitExtractElement(const User &I);
|
|
void visitInsertElement(const User &I);
|
|
void visitShuffleVector(const User &I);
|
|
|
|
void visitExtractValue(const User &I);
|
|
void visitInsertValue(const User &I);
|
|
void visitLandingPad(const LandingPadInst &LP);
|
|
|
|
void visitGetElementPtr(const User &I);
|
|
void visitSelect(const User &I);
|
|
|
|
void visitAlloca(const AllocaInst &I);
|
|
void visitLoad(const LoadInst &I);
|
|
void visitStore(const StoreInst &I);
|
|
void visitMaskedLoad(const CallInst &I, bool IsExpanding = false);
|
|
void visitMaskedStore(const CallInst &I, bool IsCompressing = false);
|
|
void visitMaskedGather(const CallInst &I);
|
|
void visitMaskedScatter(const CallInst &I);
|
|
void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
|
|
void visitAtomicRMW(const AtomicRMWInst &I);
|
|
void visitFence(const FenceInst &I);
|
|
void visitPHI(const PHINode &I);
|
|
void visitCall(const CallInst &I);
|
|
bool visitMemCmpCall(const CallInst &I);
|
|
bool visitMemPCpyCall(const CallInst &I);
|
|
bool visitMemChrCall(const CallInst &I);
|
|
bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
|
|
bool visitStrCmpCall(const CallInst &I);
|
|
bool visitStrLenCall(const CallInst &I);
|
|
bool visitStrNLenCall(const CallInst &I);
|
|
bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
|
|
bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
|
|
void visitAtomicLoad(const LoadInst &I);
|
|
void visitAtomicStore(const StoreInst &I);
|
|
void visitLoadFromSwiftError(const LoadInst &I);
|
|
void visitStoreToSwiftError(const StoreInst &I);
|
|
|
|
void visitInlineAsm(ImmutableCallSite CS);
|
|
const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
|
|
void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
|
|
void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI);
|
|
|
|
void visitVAStart(const CallInst &I);
|
|
void visitVAArg(const VAArgInst &I);
|
|
void visitVAEnd(const CallInst &I);
|
|
void visitVACopy(const CallInst &I);
|
|
void visitStackmap(const CallInst &I);
|
|
void visitPatchpoint(ImmutableCallSite CS,
|
|
const BasicBlock *EHPadBB = nullptr);
|
|
|
|
// These two are implemented in StatepointLowering.cpp
|
|
void visitGCRelocate(const GCRelocateInst &Relocate);
|
|
void visitGCResult(const GCResultInst &I);
|
|
|
|
void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
|
|
|
|
void visitUserOp1(const Instruction &I) {
|
|
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
|
|
}
|
|
void visitUserOp2(const Instruction &I) {
|
|
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
|
|
}
|
|
|
|
void processIntegerCallValue(const Instruction &I,
|
|
SDValue Value, bool IsSigned);
|
|
|
|
void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
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/// If V is an function argument then create corresponding DBG_VALUE machine
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/// instruction for it now. At the end of instruction selection, they will be
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/// inserted to the entry BB.
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bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
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DIExpression *Expr, DILocation *DL,
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bool IsDbgDeclare, const SDValue &N);
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/// Return the next block after MBB, or nullptr if there is none.
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MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
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/// Update the DAG and DAG builder with the relevant information after
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/// a new root node has been created which could be a tail call.
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void updateDAGForMaybeTailCall(SDValue MaybeTC);
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/// Return the appropriate SDDbgValue based on N.
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SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable,
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DIExpression *Expr, const DebugLoc &dl,
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unsigned DbgSDNodeOrder);
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};
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/// RegsForValue - This struct represents the registers (physical or virtual)
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/// that a particular set of values is assigned, and the type information about
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/// the value. The most common situation is to represent one value at a time,
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/// but struct or array values are handled element-wise as multiple values. The
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/// splitting of aggregates is performed recursively, so that we never have
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/// aggregate-typed registers. The values at this point do not necessarily have
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/// legal types, so each value may require one or more registers of some legal
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/// type.
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///
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struct RegsForValue {
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/// The value types of the values, which may not be legal, and
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/// may need be promoted or synthesized from one or more registers.
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SmallVector<EVT, 4> ValueVTs;
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/// The value types of the registers. This is the same size as ValueVTs and it
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/// records, for each value, what the type of the assigned register or
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/// registers are. (Individual values are never synthesized from more than one
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/// type of register.)
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///
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/// With virtual registers, the contents of RegVTs is redundant with TLI's
|
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/// getRegisterType member function, however when with physical registers
|
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/// it is necessary to have a separate record of the types.
|
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SmallVector<MVT, 4> RegVTs;
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|
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/// This list holds the registers assigned to the values.
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/// Each legal or promoted value requires one register, and each
|
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/// expanded value requires multiple registers.
|
|
SmallVector<unsigned, 4> Regs;
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|
|
|
/// This list holds the number of registers for each value.
|
|
SmallVector<unsigned, 4> RegCount;
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|
|
|
/// Records if this value needs to be treated in an ABI dependant manner,
|
|
/// different to normal type legalization.
|
|
Optional<CallingConv::ID> CallConv;
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|
|
|
RegsForValue() = default;
|
|
RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt,
|
|
Optional<CallingConv::ID> CC = None);
|
|
RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
|
|
const DataLayout &DL, unsigned Reg, Type *Ty,
|
|
Optional<CallingConv::ID> CC);
|
|
|
|
bool isABIMangled() const {
|
|
return CallConv.hasValue();
|
|
}
|
|
|
|
/// Add the specified values to this one.
|
|
void append(const RegsForValue &RHS) {
|
|
ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
|
|
RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
|
|
Regs.append(RHS.Regs.begin(), RHS.Regs.end());
|
|
RegCount.push_back(RHS.Regs.size());
|
|
}
|
|
|
|
/// Emit a series of CopyFromReg nodes that copies from this value and returns
|
|
/// the result as a ValueVTs value. This uses Chain/Flag as the input and
|
|
/// updates them for the output Chain/Flag. If the Flag pointer is NULL, no
|
|
/// flag is used.
|
|
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
|
|
const SDLoc &dl, SDValue &Chain, SDValue *Flag,
|
|
const Value *V = nullptr) const;
|
|
|
|
/// Emit a series of CopyToReg nodes that copies the specified value into the
|
|
/// registers specified by this object. This uses Chain/Flag as the input and
|
|
/// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no
|
|
/// flag is used. If V is not nullptr, then it is used in printing better
|
|
/// diagnostic messages on error.
|
|
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl,
|
|
SDValue &Chain, SDValue *Flag, const Value *V = nullptr,
|
|
ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
|
|
|
|
/// Add this value to the specified inlineasm node operand list. This adds the
|
|
/// code marker, matching input operand index (if applicable), and includes
|
|
/// the number of values added into it.
|
|
void AddInlineAsmOperands(unsigned Code, bool HasMatching,
|
|
unsigned MatchingIdx, const SDLoc &dl,
|
|
SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
|
|
|
|
/// Check if the total RegCount is greater than one.
|
|
bool occupiesMultipleRegs() const {
|
|
return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
|
|
}
|
|
|
|
/// Return a list of registers and their sizes.
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
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