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llvm-project/llvm/test/CodeGen
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Petar Avramovic 0a5e4eb776 [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM 
Add support for s64 libcalls for G_SDIV, G_UDIV, G_SREM and G_UREM
and use integer type of correct size when creating arguments for
CLI.lowerCall.
Select G_SDIV, G_UDIV, G_SREM and G_UREM for types s8, s16, s32 and s64
on MIPS32.

Differential Revision: https://reviews.llvm.org/D55651

llvm-svn: 349499
 		2018-12-18 15:59:51 +00:00
..
AArch64 [AArch64] - Return address signing dwarf support 2018-12-18 10:37:42 +00:00
AMDGPU AMDGPU: Legalize/regbankselect frame_index 2018-12-18 09:46:13 +00:00
ARC
…
ARM ARM: use acquire/release instruction variants when available. 2018-12-17 15:05:32 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF
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Generic Move llc-start-stop-instance to x86 2018-12-04 18:19:08 +00:00
Hexagon [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates 2018-12-16 14:57:04 +00:00
Inputs
…
Lanai [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
MIR [AArch64] - Return address signing dwarf support 2018-12-18 10:37:42 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM 2018-12-18 15:59:51 +00:00
NVPTX [NVPTX] Lower instructions that expand into libcalls. 2018-12-14 23:53:06 +00:00
Nios2
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PowerPC [PowerPC][NFC]Update vabsd cases with vselect test cases 2018-12-18 08:11:32 +00:00
RISCV [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
SPARC [Sparc] Use float register for integer constrained with "f" in inline asm 2018-12-13 15:13:29 +00:00
SystemZ [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorElts 2018-12-15 11:36:36 +00:00
Thumb [RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers 2018-12-14 14:07:57 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] Fix assembler parsing of br_table. 2018-12-17 22:04:44 +00:00
WinCFGuard
…
WinEH
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X86 [X86][SSE] Add shift combine 'out of range' tests with UNDEFs 2018-12-18 13:37:04 +00:00
XCore [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00