forked from OSchip/llvm-project
114 lines
4.6 KiB
MLIR
114 lines
4.6 KiB
MLIR
// RUN: mlir-opt %s -linalg-tile-to-parallel-loops="linalg-tile-sizes=2,4,8" -split-input-file | FileCheck %s
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// RUN: mlir-opt %s -linalg-tile-to-parallel-loops="linalg-tile-sizes=2" -split-input-file | FileCheck %s -check-prefix=TILE1
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// RUN: mlir-opt %s -linalg-tile-to-parallel-loops="linalg-tile-sizes=2,4" -split-input-file | FileCheck %s -check-prefix=TILE2
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func @gemm(%arg0 : memref<?x?xf32>,
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%arg1 : memref<?x?xf32>,
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%arg2 : memref<?x?xf32>)
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{
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linalg.matmul ins(%arg0, %arg1: memref<?x?xf32>, memref<?x?xf32>)
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outs(%arg2: memref<?x?xf32>)
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return
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}
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// CHECK-LABEL: func @gemm
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// CHECK-DAG: %[[C2:.*]] = constant 2 : index
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// CHECK-DAG: %[[C4:.*]] = constant 4 : index
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// CHECK-DAG: %[[C8:.*]] = constant 8 : index
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// CHECK: scf.parallel (%[[ARG3:.*]], %[[ARG4:.*]]) =
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// CHECK-SAME: step (%[[C2]], %[[C4]])
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// CHECK: scf.for %[[ARG5:.*]] =
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// CHECK-SAME: step %[[C8]]
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// CHECK: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG5]]]
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// CHECK: %[[SV2:.*]] = subview %{{.*}}[%[[ARG5]], %[[ARG4]]]
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// CHECK: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]]]
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// CHECK: linalg.matmul ins(%[[SV1]], %[[SV2]]{{.*}} outs(%[[SV3]]
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// TILE1-LABEL: func @gemm
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// TILE1-DAG: %[[C2:.*]] = constant 2 : index
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// TILE1: scf.parallel (%[[ARG3:.*]]) =
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// TILE1-SAME: step (%[[C2]])
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// TILE1: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], 0]
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// TILE1: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], 0]
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// TILE1-NOT: subview
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// TILE1: linalg.matmul ins(%[[SV1]], %{{.*}} outs(%[[SV3]]
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// TILE2-LABEL: func @gemm
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// TILE2-DAG: %[[C2:.*]] = constant 2 : index
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// TILE2-DAG: %[[C4:.*]] = constant 4 : index
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// TILE2: scf.parallel (%[[ARG3:.*]], %[[ARG4:.*]]) =
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// TILE2-SAME: step (%[[C2]], %[[C4]])
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// TILE2: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], 0]
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// TILE2: %[[SV2:.*]] = subview %{{.*}}[0, %[[ARG4]]]
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// TILE2: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]]]
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// TILE2: linalg.matmul ins(%[[SV1]], %[[SV2]]{{.*}} outs(%[[SV3]]
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// -----
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#map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
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#map1 = affine_map<(d0, d1, d2) -> (d0, d2)>
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#map2 = affine_map<(d0, d1, d2) -> (d1)>
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#accesses = [#map0, #map1, #map2]
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#trait = {
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args_in = 2 : i64,
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args_out = 1 : i64,
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iterator_types = ["reduction", "parallel", "reduction"],
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indexing_maps = #accesses
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}
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func @reduction(%arg0 : memref<?x?x?xf32>,
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%arg1 : memref<?x?xf32>,
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%arg2 : memref<?xf32>)
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{
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linalg.generic #trait
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ins(%arg0, %arg1 : memref<?x?x?xf32>, memref<?x?xf32>)
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outs(%arg2 : memref<?xf32>) {
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^bb0(%arg3 : f32, %arg4 : f32, %arg5 : f32):
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%0 = addf %arg3, %arg4 : f32
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%1 = addf %0, %arg5 : f32
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linalg.yield %1 : f32
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}
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return
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}
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// CHECK-LABEL: func @reduction
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// CHECK-DAG: %[[C2:.*]] = constant 2 : index
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// CHECK-DAG: %[[C4:.*]] = constant 4 : index
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// CHECK-DAG: %[[C8:.*]] = constant 8 : index
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// CHECK: scf.for %[[ARG3:.*]] =
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// CHECK-SAME: step %[[C2]]
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// CHECK: scf.parallel (%[[ARG4:.*]]) =
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// CHECK-SAME: step (%[[C4]])
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// CHECK: scf.for %[[ARG5:.*]] =
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// CHECK-SAME: step %[[C8]]
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// CHECK: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]], %[[ARG5]]]
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// CHECK: %[[SV2:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG5]]]
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// CHECK: %[[SV3:.*]] = subview %{{.*}}[%[[ARG4]]]
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// CHECK: linalg.generic
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// CHECK-SAME: ins(%[[SV1]], %[[SV2]]
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// CHECK-SAME: outs(%[[SV3]]
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// TILE1-LABEL: func @reduction
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// TILE1-DAG: %[[C2:.*]] = constant 2 : index
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// TILE1: scf.for %[[ARG3:.*]] =
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// TILE1-SAME: step %[[C2]]
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// TILE1: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], 0, 0]
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// TILE1: %[[SV2:.*]] = subview %{{.*}}[%[[ARG3]], 0]
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// TILE1-NOT: subview
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// TILE1: linalg.generic
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// TILE1-SAME: ins(%[[SV1]], %[[SV2]]
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// TILE1-SAME: outs(%{{.*}}
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// TILE2-LABEL: func @reduction
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// TILE2-DAG: %[[C2:.*]] = constant 2 : index
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// TILE2-DAG: %[[C4:.*]] = constant 4 : index
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// TILE2: scf.for %[[ARG3:.*]] =
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// TILE2-SAME: step %[[C2]]
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// TILE2: scf.parallel (%[[ARG4:.*]]) =
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// TILE2-SAME: step (%[[C4]])
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// TILE2: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]], 0]
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// TILE2: %[[SV2:.*]] = subview %{{.*}}[%[[ARG3]], 0]
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// TILE2: %[[SV3:.*]] = subview %{{.*}}[%[[ARG4]]]
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// TILE2: linalg.generic
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// TILE2-SAME: ins(%[[SV1]], %[[SV2]]
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// TILE2-SAME: outs(%[[SV3]]
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