forked from OSchip/llvm-project
70 lines
3.3 KiB
LLVM
70 lines
3.3 KiB
LLVM
; RUN: opt %loadPolly -basicaa -polly-scops -analyze < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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;long f(long a[], long n) {
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; long i, k;
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; k = 1;
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; for (i = 1; i < n; ++i) {
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; a[i] = k * a[i - 1];
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; k = a[i + 3] + a[2 * i];
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; }
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; return 0;
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;}
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define i64 @f(i64* nocapture %a, i64 %n) nounwind {
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entry:
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%0 = icmp sgt i64 %n, 1 ; <i1> [#uses=1]
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br i1 %0, label %bb.nph, label %bb2
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bb.nph: ; preds = %entry
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%tmp = add i64 %n, -1 ; <i64> [#uses=1]
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%.pre = load i64, i64* %a, align 8 ; <i64> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%tmp1 = phi i64 [ %.pre, %bb.nph ], [ %tmp2, %bb ] ; <i64> [#uses=1]
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%indvar = phi i64 [ 0, %bb.nph ], [ %tmp6, %bb ] ; <i64> [#uses=3]
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%k.05 = phi i64 [ 1, %bb.nph ], [ %tmp5, %bb ] ; <i64> [#uses=1]
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%tmp6 = add i64 %indvar, 1 ; <i64> [#uses=3]
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%scevgep = getelementptr i64, i64* %a, i64 %tmp6 ; <i64*> [#uses=1]
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%tmp2 = mul nsw i64 %tmp1, %k.05 ; <i64> [#uses=2]
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store i64 %tmp2, i64* %scevgep, align 8
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%tmp7 = shl i64 %indvar, 1 ; <i64> [#uses=1]
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%tmp11 = add i64 %indvar, 4 ; <i64> [#uses=1]
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%tmp8 = add i64 %tmp7, 2 ; <i64> [#uses=1]
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%scevgep12 = getelementptr i64, i64* %a, i64 %tmp11 ; <i64*> [#uses=1]
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%scevgep9 = getelementptr i64, i64* %a, i64 %tmp8 ; <i64*> [#uses=1]
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%tmp3 = load i64, i64* %scevgep9, align 8 ; <i64> [#uses=1]
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%tmp4 = load i64, i64* %scevgep12, align 8 ; <i64> [#uses=1]
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%tmp5 = add nsw i64 %tmp3, %tmp4 ; <i64> [#uses=1]
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%exitcond = icmp eq i64 %tmp6, %tmp ; <i1> [#uses=1]
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br i1 %exitcond, label %bb2, label %bb
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bb2: ; preds = %bb, %entry
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ret i64 0
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}
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; CHECK: Statements {
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; CHECK-NEXT: Stmt_bb
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] : 0 <= i0 <= -2 + n };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> [i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_tmp1__phi[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_tmp1__phi[] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_k_05__phi[] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_k_05__phi[] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_a[1 + i0] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_a[2 + 2i0] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [n] -> { Stmt_bb[i0] -> MemRef_a[4 + i0] };
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; CHECK-NEXT: }
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