llvm-project/llvm/test/MachineVerifier
Roman Lebedev 3f1f08f0ed
Revert @llvm.isnan intrinsic patchset.
Please refer to
https://lists.llvm.org/pipermail/llvm-dev/2021-September/152440.html
(and that whole thread.)

TLDR: the original patch had no prior RFC, yet it had some changes that
really need a proper RFC discussion. It won't be productive to discuss
such an RFC, once it's actually posted, while said patch is already
committed, because that introduces bias towards already-committed stuff,
and the tree is potentially in broken state meanwhile.

While the end result of discussion may lead back to the current design,
it may also not lead to the current design.

Therefore i take it upon myself
to revert the tree back to last known good state.

This reverts commit 4c4093e6e3.
This reverts commit 0a2b1ba33a.
This reverts commit d9873711cb.
This reverts commit 791006fb8c.
This reverts commit c22b64ef66.
This reverts commit 72ebcd3198.
This reverts commit 5fa6039a5f.
This reverts commit 9efda541bf.
This reverts commit 94d3ff09cf.
2021-09-02 13:53:56 +03:00
..
generic-vreg-undef-use.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
live-ins-01.mir
live-ins-02.mir
live-ins-03.mir
test_copy.mir
test_copy_mismatch_types.mir
test_copy_physregs_x86.mir [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
test_g_add.mir
test_g_addrspacecast.mir
test_g_assert_sext.mir
test_g_assert_sext_register_bank_class.mir
test_g_assert_zext.mir
test_g_assert_zext_register_bank_class.mir
test_g_bitcast.mir
test_g_brindirect_is_indirect_branch.mir
test_g_brjt.mir
test_g_brjt_is_indirect_branch.mir
test_g_build_vector.mir
test_g_build_vector_trunc.mir
test_g_bzero.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_concat_vectors.mir
test_g_constant.mir
test_g_dyn_stackalloc.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_icmp.mir
test_g_insert.mir
test_g_intrinsic.mir
test_g_intrinsic_w_side_effects.mir
test_g_inttoptr.mir
test_g_jump_table.mir
test_g_llround.mir [GlobalISel] Add G_LLROUND 2021-08-20 14:07:21 -07:00
test_g_load.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_lround.mir [GlobalISel] Add G_LLROUND 2021-08-20 14:07:21 -07:00
test_g_memcpy.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_memcpy_inline.mir [GISel] Support llvm.memcpy.inline 2021-06-30 12:39:05 -07:00
test_g_memmove.mir [GISel] Support llvm.memcpy.inline 2021-06-30 12:39:05 -07:00
test_g_memset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_merge_values.mir
test_g_phi.mir
test_g_ptr_add.mir
test_g_ptrmask.mir
test_g_ptrtoint.mir
test_g_rotr_rotl.mir
test_g_select.mir
test_g_sext_inreg.mir
test_g_sextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_shuffle_vector.mir
test_g_store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_g_trunc.mir
test_g_ubfx_sbfx.mir
test_g_zextload.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
test_insert_subreg.mir [MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs 2021-07-21 08:47:17 -07:00
test_phis_precede_nonphis.mir
test_vector_reductions.mir [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization. 2021-08-19 16:38:52 -07:00
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir
verifier-phi-fail0.mir
verifier-phi.mir
verifier-pseudo-terminators.mir
verifier-statepoint.mir
verify-regbankselected.mir
verify-regops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-selected.mir