forked from OSchip/llvm-project
41 lines
1.5 KiB
LLVM
41 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
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; Regression test for an issue in which DAG combines created a constant i8x16
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; vector with lane values of 255, which was outside the -128 to 127 range
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; expected by our ISel patterns (and similar for the i16 version) and caused an
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; ISel failure. The fix was to adjust out-of-range values manually in
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; BUILD_VECTOR lowering.
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target triple = "wasm32-unknown-unknown"
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define <4 x i8> @test_i8(<4 x i8> %b) {
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; CHECK-LABEL: test_i8:
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; CHECK: .functype test_i8 (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.const -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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; CHECK-NEXT: v128.xor
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; CHECK-NEXT: v128.const 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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; CHECK-NEXT: v128.and
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; CHECK-NEXT: # fallthrough-return
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%c = and <4 x i8> %b, <i8 1, i8 1, i8 1, i8 1>
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%d = xor <4 x i8> %c, <i8 1, i8 1, i8 1, i8 1>
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ret <4 x i8> %d
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}
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define <4 x i16> @test_i16(<4 x i16> %b) {
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; CHECK-LABEL: test_i16:
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; CHECK: .functype test_i16 (v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: v128.const -1, -1, -1, -1, 0, 0, 0, 0
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; CHECK-NEXT: v128.xor
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; CHECK-NEXT: v128.const 1, 1, 1, 1, 0, 0, 0, 0
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; CHECK-NEXT: v128.and
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; CHECK-NEXT: # fallthrough-return
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%c = and <4 x i16> %b, <i16 1, i16 1, i16 1, i16 1>
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%d = xor <4 x i16> %c, <i16 1, i16 1, i16 1, i16 1>
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ret <4 x i16> %d
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}
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