forked from OSchip/llvm-project
232 lines
8.0 KiB
LLVM
232 lines
8.0 KiB
LLVM
; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
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; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
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; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
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; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
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; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE --check-prefix=CHECK-XO-DOUBLE-BE-FPREGS %s
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; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m3 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-DOUBLE-BE %s
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; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s
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; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
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; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
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; RUN: llc -mtriple=thumbv8m.maineb -mattr=+execute-only -mattr=fp-armv8 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s
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; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 -relocation-model=ropi %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s
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define arm_aapcs_vfpcc float @test_vmov_f32() {
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; CHECK-LABEL: test_vmov_f32:
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; CHECK: vmov.f32 d0, #1.0
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; CHECK-NONEONFP: vmov.f32 s0, #1.0
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ret float 1.0
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}
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define arm_aapcs_vfpcc float @test_vmov_imm() {
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; CHECK-LABEL: test_vmov_imm:
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; CHECK: vmov.i32 d0, #0
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; CHECK-NONEON-LABEL: test_vmov_imm:
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; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NO-XO-LABEL: test_vmov_imm:
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; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-FLOAT-LABEL: test_vmov_imm:
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; CHECK-XO-FLOAT: movs [[REG:r[0-9]+]], #0
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; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
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; CHECK-XO-FLOAT-NOT: vldr
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ret float 0.0
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}
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define arm_aapcs_vfpcc float @test_vmvn_imm() {
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; CHECK-LABEL: test_vmvn_imm:
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; CHECK: vmvn.i32 d0, #0xb0000000
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; CHECK-NONEON-LABEL: test_vmvn_imm:
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; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NO-XO-LABEL: test_vmvn_imm:
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; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-FLOAT-LABEL: test_vmvn_imm:
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; CHECK-XO-FLOAT: mvn [[REG:r[0-9]+]], #-1342177280
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; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
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; CHECK-XO-FLOAT-NOT: vldr
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ret float 8589934080.0
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}
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define arm_aapcs_vfpcc double @test_vmov_f64() {
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; CHECK-LABEL: test_vmov_f64:
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; CHECK: vmov.f64 d0, #1.0
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; CHECK-NONEON-LABEL: test_vmov_f64:
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; CHECK-NONEON: vmov.f64 d0, #1.0
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ret double 1.0
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}
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define arm_aapcs_vfpcc double @test_vmov_double_imm() {
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; CHECK-LABEL: test_vmov_double_imm:
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; CHECK: vmov.i32 d0, #0
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; CHECK-NONEON-LABEL: test_vmov_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NO-XO-LABEL: test_vmov_double_imm:
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; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-DOUBLE-LABEL: test_vmov_double_imm:
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; CHECK-XO-DOUBLE: movs [[REG:r[0-9]+]], #0
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; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
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; CHECK-XO-DOUBLE-NOT: vldr
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; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm:
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; CHECK-XO-DOUBLE-BE-FPREGS: movs [[REG:r[0-9]+]], #0
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; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]]
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; CHECK-XO-DOUBLE-NOT: vldr
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ret double 0.0
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}
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define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
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; CHECK-LABEL: test_vmvn_double_imm:
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; CHECK: vmvn.i32 d0, #0xb0000000
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; CHECK-NONEON-LABEL: test_vmvn_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NO-XO-LABEL: test_vmvn_double_imm:
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; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-DOUBLE-LABEL: test_vmvn_double_imm:
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; CHECK-XO-DOUBLE: mvn [[REG:r[0-9]+]], #-1342177280
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; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
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; CHECK-XO-DOUBLE-NOT: vldr
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; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm:
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; CHECK-XO-DOUBLE-BE-FPREGS: mvn [[REG:r[0-9]+]], #-1342177280
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; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]]
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; CHECK-XO-DOUBLE-BE-NOT: vldr
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ret double 0x4fffffff4fffffff
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}
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; Make sure we don't ignore the high half of 64-bit values when deciding whether
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; a vmov/vmvn is possible.
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define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
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; CHECK-LABEL: test_notvmvn_double_imm:
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; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NONEON-LABEL: test_notvmvn_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NO-XO-LABEL: test_notvmvn_double_imm:
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; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-DOUBLE-LABEL: test_notvmvn_double_imm:
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; CHECK-XO-DOUBLE: mvn [[REG1:r[0-9]+]], #-1342177280
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; CHECK-XO-DOUBLE: mov.w [[REG2:r[0-9]+]], #-1
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; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
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; CHECK-XO-DOUBLE-NOT: vldr
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; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm:
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; CHECK-XO-DOUBLE-BE: mvn [[REG1:r[0-9]+]], #-1342177280
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; CHECK-XO-DOUBLE-BE: mov.w [[REG2:r[0-9]+]], #-1
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; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
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; CHECK-XO-DOUBLE-BE-NOT: vldr
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ret double 0x4fffffffffffffff
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}
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define arm_aapcs_vfpcc float @lower_const_f32_xo() {
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; CHECK-NO-XO-LABEL: lower_const_f32_xo
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; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-FLOAT-LABEL: lower_const_f32_xo
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; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], #29884
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; CHECK-XO-FLOAT: movt [[REG]], #16083
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; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]]
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; CHECK-XO-FLOAT-NOT: vldr
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ret float 0x3FDA6E9780000000
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}
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define arm_aapcs_vfpcc double @lower_const_f64_xo() {
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; CHECK-NO-XO-LABEL: lower_const_f64_xo
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; CHECK-NO-XO: vldr {{d[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-XO-DOUBLE-LABEL: lower_const_f64_xo
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; CHECK-XO-DOUBLE: movw [[REG1:r[0-9]+]], #6291
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; CHECK-XO-DOUBLE: movw [[REG2:r[0-9]+]], #27263
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; CHECK-XO-DOUBLE: movt [[REG1]], #16340
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; CHECK-XO-DOUBLE: movt [[REG2]], #29884
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; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
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; CHECK-XO-DOUBLE-NOT: vldr
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; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo
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; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #6291
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; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #27263
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; CHECK-XO-DOUBLE-BE: movt [[REG1]], #16340
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; CHECK-XO-DOUBLE-BE: movt [[REG2]], #29884
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; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
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; CHECK-XO-DOUBLE-BE-NOT: vldr
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ret double 3.140000e-01
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}
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; This is a target independent optimization, performed by the
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; DAG Combiner, which promotes floating point literals into
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; constant pools:
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;
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; (a cond b) ? 1.0f : 2.0f -> load (ConstPoolAddr + ((a cond b) ? 0 : 4)
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;
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; We need to make sure that the constant pools are placed in
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; the data section when generating execute-only code:
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define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) {
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; CHECK-NO-XO-LABEL: lower_fpconst_select
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; CHECK-NO-XO: adr [[REG:r[0-9]+]], [[LABEL:.?LCPI[0-9]+_[0-9]+]]
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; CHECK-NO-XO: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
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; CHECK-NO-XO-NOT: .rodata
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; CHECK-NO-XO: [[LABEL]]:
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; CHECK-NO-XO: .long 0x4f9502f9
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; CHECK-NO-XO: .long 0x4dee6b28
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; CHECK-XO-FLOAT-LABEL: lower_fpconst_select
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; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], :lower16:[[LABEL:.?LCP[0-9]+_[0-9]+]]
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; CHECK-XO-FLOAT: movt [[REG]], :upper16:[[LABEL]]
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; CHECK-XO-FLOAT: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
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; CHECK-XO-FLOAT: .rodata
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; CHECK-XO-FLOAT-NOT: .text
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; CHECK-XO-FLOAT: [[LABEL]]:
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; CHECK-XO-FLOAT: .long 0x4f9502f9
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; CHECK-XO-FLOAT: .long 0x4dee6b28
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; CHECK-XO-ROPI-LABEL: lower_fpconst_select
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; CHECK-XO-ROPI: movw [[REG:r[0-9]+]], :lower16:([[LABEL1:.?LCP[0-9]+_[0-9]+]]-([[LABEL2:.?LPC[0-9]+_[0-9]+]]+4))
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; CHECK-XO-ROPI: movt [[REG]], :upper16:([[LABEL1]]-([[LABEL2]]+4))
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; CHECK-XO-ROPI: [[LABEL2]]:
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; CHECK-XO-ROPI: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
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; CHECK-XO-ROPI: .rodata
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; CHECK-XO-ROPI-NOT: .text
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; CHECK-XO-ROPI: [[LABEL1]]:
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; CHECK-XO-ROPI: .long 0x4f9502f9
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; CHECK-XO-ROPI: .long 0x4dee6b28
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%cmp = fcmp nnan oeq float %f, 0.000000e+00
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%sel = select i1 %cmp, float 5.000000e+08, float 5.000000e+09
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ret float %sel
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}
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