llvm-project/llvm/lib/CodeGen
Kazu Hirata c9fca53af1 [CodeGen, Target] Use pred_empty and succ_empty (NFC) 2021-09-10 11:11:31 -07:00
..
AsmPrinter [DebugInfo] Emit DW_AT_inline under -g1/-gmlt 2021-09-09 18:59:50 -07:00
GlobalISel [CallLowering] Support opaque pointers 2021-09-10 18:32:12 +02:00
LiveDebugValues [LiveDebugValues] Handle spills of indirect debug values correctly 2021-09-08 14:06:08 +03:00
MIRParser Revert "[DebugInfo] Enforce implicit constraints on `distinct` MDNodes" 2021-07-02 15:57:07 -07:00
SelectionDAG [SelectionDAG] PromoteIntRes_EXTRACT_SUBVECTOR for scalable vectors (widening). 2021-09-10 13:29:26 +01:00
AggressiveAntiDepBreaker.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-15 14:46:11 -08:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp [NFC][regalloc] Unit test for AllocationOrder iteration. 2020-09-29 10:48:07 -07:00
AllocationOrder.h [NFC] Use [MC]Register in RegAllocGreedy 2020-10-23 11:30:53 -07:00
Analysis.cpp IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
AtomicExpandPass.cpp [Remarks] [AMDGPU] Emit optimization remarks for atomics generating hardware instructions 2021-08-19 20:51:19 -06:00
BasicBlockSections.cpp Explain the symbols of basic block clusters with an example in the header comments. 2021-07-30 12:08:04 -07:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp [CodeGen, Target] Use pred_empty and succ_empty (NFC) 2021-09-10 11:11:31 -07:00
BranchFolding.h Fix some clang-tidy bugprone-argument-comment issues 2020-09-19 20:41:25 -07:00
BranchRelaxation.cpp [AArch64] Enable implicit null check transformation 2020-09-17 16:00:19 -07:00
BreakFalseDeps.cpp [NFC][MC] Use MCRegister for ReachingDefAnalysis APIs 2020-10-22 08:47:35 -07:00
CFGuardLongjmp.cpp
CFIInstrInserter.cpp Implement DW_CFA_LLVM_* for Heterogeneous Debugging 2021-06-14 08:51:50 +05:30
CMakeLists.txt [SampleFDO] Flow Sensitive Sample FDO (FSAFDO) profile loader 2021-08-18 18:37:35 -07:00
CalcSpillWeights.cpp [RegAlloc] Fix "ran out of regs" with uses in statepoint 2021-03-24 10:25:34 +07:00
CallingConvLower.cpp [SVE] Deal with SVE tuple call arguments correctly when running out of registers 2020-11-12 08:41:50 +00:00
CodeGen.cpp [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-14 04:29:42 -07:00
CodeGenPassBuilder.cpp Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to help build codegen pipeline" (again) 2020-12-29 16:39:55 -08:00
CodeGenPrepare.cpp [CGP] Fix the crash for combining address mode when having cyclic dependency 2021-08-26 22:52:42 +08:00
CommandFlags.cpp [NFC] More get/removeAttribute() cleanup 2021-08-17 21:05:41 -07:00
CriticalAntiDepBreaker.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
DeadMachineInstructionElim.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
DetectDeadLanes.cpp [NFC] Reflow some debug messages. 2021-07-27 10:11:51 +01:00
DwarfEHPrepare.cpp [NFC] [DwarfEHPrepare] Add additional stats for EH 2021-06-23 17:09:30 -07:00
EHContGuardCatchret.cpp Add ehcont section support 2021-02-15 14:27:12 +08:00
EarlyIfConversion.cpp [EarlyIfConversion] Avoid producing selects with identical operands 2021-04-30 15:51:14 -07:00
EdgeBundles.cpp [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
ExecutionDomainFix.cpp ExecutionDomainFix.cpp - use const refs in for-range loops. NFCI. 2021-01-27 15:39:32 +00:00
ExpandMemCmp.cpp [ExpandMemCmpPass] Preserve Dominator Tree, if available 2021-01-30 01:14:51 +03:00
ExpandPostRAPseudos.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-12 23:44:33 -08:00
ExpandReductions.cpp [ExpandReductions] fix FMF requirement for fmin/fmax 2021-02-04 13:32:08 -05:00
ExpandVectorPredication.cpp [VP] Add vector-predicated reduction intrinsics 2021-08-17 17:56:35 +01:00
FEntryInserter.cpp
FaultMaps.cpp [FaultsMaps][llvm-objdump] Move FaultMapParser to Object/. Remove CodeGen dependency from llvm-objdump 2021-01-27 10:39:59 -08:00
FinalizeISel.cpp
FixupStatepointCallerSaved.cpp [llvm][clang][NFC] updates inline licence info 2021-08-11 02:48:53 +00:00
FuncletLayout.cpp
GCMetadata.cpp [GC][NFC] Make getGCStrategy by name available in IR 2021-08-02 14:26:04 +07:00
GCMetadataPrinter.cpp
GCRootLowering.cpp [AMDGPU] Disable garbage collection passes 2021-07-07 15:47:57 -07:00
GlobalMerge.cpp [SVE][CodeGen] Replace use of TypeSize operator< in GlobalMerge::doMerge 2020-10-01 14:06:59 +01:00
HardwareLoops.cpp Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount." 2021-09-03 02:55:43 +00:00
IfConversion.cpp [IfCvt] Don't use pristine register for counting liveins for predicated instructions. 2021-07-11 14:45:54 +01:00
ImplicitNullChecks.cpp [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. 2021-04-09 12:54:22 +03:00
IndirectBrExpandPass.cpp [CodeGen] IndirectBrExpandPass: preserve Dominator Tree, if available 2021-01-28 01:58:53 +03:00
InlineSpiller.cpp [GreedyRA] Add support for invoke statepoint with tied-defs. 2021-05-05 11:13:35 +07:00
InterferenceCache.cpp [NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache 2020-10-07 14:48:43 -07:00
InterferenceCache.h [NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache 2020-10-07 14:48:43 -07:00
InterleavedAccessPass.cpp [InterleaveAccess] Copy fast math flags when adjusting binary operators in interleave access pass 2021-06-17 09:53:33 +01:00
InterleavedLoadCombinePass.cpp [APInt] Normalize naming on keep constructors / predicate methods. 2021-09-09 09:50:24 -07:00
IntrinsicLowering.cpp Introduce llvm.noalias.decl intrinsic 2021-01-16 09:20:45 +01:00
LLVMTargetMachine.cpp [AIX] Use AsmParser to do inline asm parsing 2021-07-02 16:12:21 +00:00
LatencyPriorityQueue.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
LazyMachineBlockFrequencyInfo.cpp
LexicalScopes.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LiveDebugVariables.cpp [DebugInfo][InstrRef] Don't use instr-ref for unoptimised functions 2021-08-25 15:10:36 +01:00
LiveDebugVariables.h [LiveDebugVariables] Delete unneeded doInitialization 2020-09-04 13:27:42 -07:00
LiveInterval.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-21 19:58:07 -08:00
LiveIntervalCalc.cpp [llvm] Ensure newlines at the end of files (NFC) 2021-01-10 09:24:57 -08:00
LiveIntervalUnion.cpp [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration 2021-04-01 08:33:28 -07:00
LiveIntervals.cpp RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
LivePhysRegs.cpp [IfCvt] Don't use pristine register for counting liveins for predicated instructions. 2021-07-11 14:45:54 +01:00
LiveRangeCalc.cpp [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-29 23:23:36 -08:00
LiveRangeEdit.cpp [RegAlloc] Immediately delete dead instructions with live uses 2021-08-31 13:46:00 -07:00
LiveRangeShrink.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LiveRangeUtils.h [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
LiveRegMatrix.cpp [regalloc] Ensure Query::collectInterferringVregs is called before interval iteration 2021-04-01 08:33:28 -07:00
LiveRegUnits.cpp [ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded 2021-01-28 09:22:55 +00:00
LiveStacks.cpp
LiveVariables.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
LocalStackSlotAllocation.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-13 20:41:39 -08:00
LoopTraversal.cpp
LowLevelType.cpp GlobalISel: Add helper function for getting EVT from LLT 2021-08-13 21:10:13 -04:00
LowerEmuTLS.cpp [LowerEmuTls] Copy dso_local from <var> to __emutls_v.<var> 2020-12-30 16:11:32 -08:00
MBFIWrapper.cpp [ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC) 2021-06-03 18:34:36 +02:00
MIRCanonicalizerPass.cpp [CodeGen] Use llvm::append_range (NFC) 2021-01-21 19:59:46 -08:00
MIRFSDiscriminator.cpp [SampleFDO] Place the discriminator flag variable into the used list. 2021-06-15 21:51:04 -07:00
MIRNamerPass.cpp
MIRPrinter.cpp [Debug-info][InstrRef] Avoid an unnecessary map ordering 2021-07-09 15:43:13 +01:00
MIRPrintingPass.cpp
MIRSampleProfile.cpp Move function definition out-of-line to fix the modularized build (NFC) 2021-08-19 12:26:23 -07:00
MIRVRegNamerUtils.cpp Rename MachineMemOperand::getOrdering -> getSuccessOrdering. 2021-06-21 16:49:27 -07:00
MIRVRegNamerUtils.h
MIRYamlMapping.cpp [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
MachineBasicBlock.cpp [CSSPGO] Undoing the concept of dangling pseudo probe 2021-06-18 15:14:11 -07:00
MachineBlockFrequencyInfo.cpp CodeGen: Fix null dereference before null check 2021-05-11 09:07:32 -04:00
MachineBlockPlacement.cpp [CodeGen, Target] Use pred_empty and succ_empty (NFC) 2021-09-10 11:11:31 -07:00
MachineBranchProbabilityInfo.cpp [Analaysis, CodeGen] Remove getHotSucc (NFC) 2021-07-17 07:31:36 -07:00
MachineCSE.cpp [MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs 2021-05-05 14:22:03 -07:00
MachineCheckDebugify.cpp [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
MachineCombiner.cpp [PowerPC] support register pressure reduction in machine combiner. 2021-01-24 21:28:21 -05:00
MachineCopyPropagation.cpp [MachineCopyPropagation] Check CrossCopyRegClass for cross-class copys 2021-08-24 21:22:36 -07:00
MachineDebugify.cpp [Debugify] Support checking Machine IR debug info 2020-12-16 22:17:25 -08:00
MachineDominanceFrontier.cpp
MachineDominators.cpp
MachineFrameInfo.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
MachineFunction.cpp [DebugInfo][InstrRef] Don't use instr-ref for unoptimised functions 2021-08-25 15:10:36 +01:00
MachineFunctionPass.cpp [NFC] Reduce include files dependency. 2020-12-03 18:25:05 +03:00
MachineFunctionPrinterPass.cpp [NewPM] Support --print-before/after in NPM 2020-12-03 16:52:14 -08:00
MachineFunctionSplitter.cpp [NFC] Use hasSection instead of getSection().empty() 2021-04-23 10:00:38 -07:00
MachineInstr.cpp [clang] Use i64 for the !srcloc metadata on asm IR nodes. 2021-07-22 10:24:52 +01:00
MachineInstrBundle.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-15 14:46:11 -08:00
MachineLICM.cpp Prevent machine licm if remattable with a vreg use 2021-08-16 12:09:00 -07:00
MachineLoopInfo.cpp [ARM] Allow findLoopPreheader to return headers with multiple loop successors 2021-05-24 12:22:15 +01:00
MachineLoopUtils.cpp [CodeGen] Remove unused function isRegLiveInExitBlocks (NFC) 2021-01-12 21:43:48 -08:00
MachineModuleInfo.cpp [MC] Refactor MCObjectFileInfo initialization and allow targets to create MCObjectFileInfo 2021-05-23 14:15:23 -07:00
MachineModuleInfoImpls.cpp [WebAssembly] Added initial type checker to MC Assembler 2021-07-09 14:07:25 -07:00
MachineModuleSlotTracker.cpp [MIRPrinter] Add machine metadata support. 2021-06-19 12:48:08 -04:00
MachineOperand.cpp [WebAssembly] Implementation of global.get/set for reftypes in LLVM IR 2021-07-22 22:07:24 +02:00
MachineOptimizationRemarkEmitter.cpp CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis 2021-07-19 21:08:26 -04:00
MachineOutliner.cpp Add the use of register r for outlined function when register r is live in and defined later. 2021-03-03 15:14:11 -08:00
MachinePassManager.cpp [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose 2021-05-07 21:51:47 -07:00
MachinePipeliner.cpp [NFC] Clean up users of AttributeList::hasAttribute() 2021-08-13 11:59:18 -07:00
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp [AIX][XCOFF] emit vector info of traceback table. 2021-06-14 11:15:22 -04:00
MachineSSAUpdater.cpp [docs] Fix doxygen comments wrongly attached to the llvm namespace 2021-04-07 01:20:18 +02:00
MachineScheduler.cpp [MachineScheduler] Fix tracing 2021-08-26 09:27:01 +01:00
MachineSink.cpp [DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes 2021-07-08 16:42:24 +01:00
MachineSizeOpts.cpp
MachineStableHash.cpp Rename MachineMemOperand::getOrdering -> getSuccessOrdering. 2021-06-21 16:49:27 -07:00
MachineStripDebug.cpp
MachineTraceMetrics.cpp [NFC][MC] Type [MC]Register uses in MachineTraceMetrics 2020-10-19 09:49:52 -07:00
MachineVerifier.cpp [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
MacroFusion.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
ModuloSchedule.cpp [ModuloSchedule] Pass loop block explicitly to kernel rewriter. 2021-06-25 09:51:22 -07:00
MultiHazardRecognizer.cpp [CodeGen, Transforms] Use llvm::any_of (NFC) 2020-12-24 09:08:36 -08:00
NonRelocatableStringpool.cpp
OptimizePHIs.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
PHIElimination.cpp [DebugInstrRef][1/3] Track PHI values through register allocation 2021-05-26 20:24:00 +01:00
PHIEliminationUtils.cpp PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR. 2020-09-18 14:14:04 -04:00
PHIEliminationUtils.h
ParallelCG.cpp [LTO] Update splitCodeGen to take a reference to the module. (NFC) 2021-01-29 11:53:11 +00:00
PatchableFunction.cpp
PeepholeOptimizer.cpp [InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI) 2021-08-30 19:46:04 +02:00
PostRAHazardRecognizer.cpp [HazardRec] Allow inserting multiple wait-states simultaneously 2020-10-20 17:03:47 -07:00
PostRASchedulerList.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
PreISelIntrinsicLowering.cpp [CodeGen] Construct SmallVector with iterator ranges (NFC) 2020-12-31 09:39:11 -08:00
ProcessImplicitDefs.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
PrologEpilogInserter.cpp Handle subregs and superregs in callee-saved register mask 2021-07-29 16:53:29 +01:00
PseudoProbeInserter.cpp [CSSPGO] Undoing the concept of dangling pseudo probe 2021-06-18 15:14:11 -07:00
PseudoSourceValue.cpp
RDFGraph.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-17 23:58:46 -08:00
RDFLiveness.cpp Fix a range-loop-analysis warning. 2021-02-23 14:41:08 -08:00
RDFRegisters.cpp [NFC][MC] Use MCRegister for ReachingDefAnalysis APIs 2020-10-22 08:47:35 -07:00
README.txt
ReachingDefAnalysis.cpp [RDA] Attempt to make RDA subreg aware 2021-08-04 14:21:32 +01:00
RegAllocBase.cpp RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
RegAllocBase.h RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
RegAllocBasic.cpp RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
RegAllocFast.cpp RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
RegAllocGreedy.cpp [RegAlloc] Remove addAllocPriorityToGlobalRanges hook 2021-08-18 10:21:27 +08:00
RegAllocPBQP.cpp [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text 2021-04-06 07:23:31 -04:00
RegUsageInfoCollector.cpp
RegUsageInfoPropagate.cpp RegUsageInfoPropagate.cpp - remove unused <string> and <map> includes. NFCI. 2021-06-13 15:19:24 +01:00
RegisterClassInfo.cpp Support a list of CostPerUse values 2021-01-29 10:14:52 +05:30
RegisterCoalescer.cpp [RegisterCoalescer] Make resolveConflicts aware of earlyclobber 2021-07-22 12:11:10 +08:00
RegisterCoalescer.h [NFC] Use [MC]Register in RegAllocPBQP & RegisterCoalescer 2020-10-26 17:13:32 -07:00
RegisterPressure.cpp [DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes 2021-07-08 16:42:24 +01:00
RegisterScavenging.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
RegisterUsageInfo.cpp
RemoveRedundantDebugValues.cpp [2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-15 00:08:31 -07:00
RenameIndependentSubregs.cpp [NFC][Regalloc] accessors for 'reg' and 'weight' 2020-09-16 08:28:57 -07:00
ReplaceWithVeclib.cpp Intrinsic::getName: require a Module argument 2021-06-14 14:52:29 +02:00
ResetMachineFunctionPass.cpp
SafeStack.cpp [OpaquePtr] Clean up some uses of Type::getPointerElementType() 2021-05-31 09:54:57 -07:00
SafeStackLayout.cpp [llvm] Use the default value of drop_begin (NFC) 2021-01-18 10:16:36 -08:00
SafeStackLayout.h
ScheduleDAG.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
ScheduleDAGInstrs.cpp [DebugInfo][InstrRef] Correctly update DBG_PHIs during instr scheduling 2021-07-27 15:12:46 +01:00
ScheduleDAGPrinter.cpp [DDG] Data Dependence Graph - DOT printer - recommit 2020-12-16 12:37:36 -05:00
ScoreboardHazardRecognizer.cpp
ShadowStackGCLowering.cpp [AMDGPU] Disable garbage collection passes 2021-07-07 15:47:57 -07:00
ShrinkWrap.cpp [ShrinkWrap] Delete unneeded nullptr checks for the save point. NFC 2020-10-22 00:27:01 -07:00
SjLjEHPrepare.cpp [SjLj] Insert UnregisterFn before musttail call 2021-06-23 15:33:55 -07:00
SlotIndexes.cpp [CSSPGO] Exclude pseudo probes from slot index 2021-04-19 17:55:35 -07:00
SpillPlacement.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-18 22:46:43 -08:00
SpillPlacement.h [regalloc] Add a couple of dump routines for ease of debugging [NFC] 2021-02-18 08:50:00 -08:00
SplitKit.cpp SplitKit: Don't further split subrange mask in buildCopy 2021-08-13 07:36:38 +08:00
SplitKit.h [GreedyRA] Add support for invoke statepoint with tied-defs. 2021-05-05 11:13:35 +07:00
StackColoring.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-19 22:44:14 -08:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions 2021-03-30 17:31:39 +01:00
StackProtector.cpp [IR] make stack-protector-guard-* flags into module attrs 2021-05-21 15:53:30 -07:00
StackSlotColoring.cpp [DebugInfo][InstrRef] Avoid stack-slot-coloring changing codegen due to DI 2021-08-25 12:04:59 +01:00
SwiftErrorValueTracking.cpp [CodeGen, DebugInfo] Use llvm::find_if (NFC) 2021-01-10 09:24:53 -08:00
SwitchLoweringUtils.cpp [APInt] Normalize naming on keep constructors / predicate methods. 2021-09-09 09:50:24 -07:00
TailDuplication.cpp
TailDuplicator.cpp [DebugInfo] Correctly update debug users of SSA values in tail duplication 2021-07-26 17:27:57 +01:00
TargetFrameLoweringImpl.cpp [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
TargetInstrInfo.cpp Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
TargetLoweringBase.cpp Revert @llvm.isnan intrinsic patchset. 2021-09-02 13:53:56 +03:00
TargetLoweringObjectFileImpl.cpp [APInt] Normalize naming on keep constructors / predicate methods. 2021-09-09 09:50:24 -07:00
TargetOptionsImpl.cpp
TargetPassConfig.cpp [SampleFDO] Flow Sensitive Sample FDO (FSAFDO) profile loader 2021-08-18 18:37:35 -07:00
TargetRegisterInfo.cpp [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. 2021-05-12 14:09:05 +01:00
TargetSchedule.cpp
TargetSubtargetInfo.cpp
TwoAddressInstructionPass.cpp [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB 2021-07-16 10:16:03 -07:00
TypePromotion.cpp [APInt] Normalize naming on keep constructors / predicate methods. 2021-09-09 09:50:24 -07:00
UnreachableBlockElim.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-20 21:46:02 -08:00
ValueTypes.cpp [AArch64] Add a Machine Value Type for 8 consecutive registers 2021-07-31 09:51:28 +01:00
VirtRegMap.cpp [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
WasmEHPrepare.cpp [WebAssembly] Extract longjmp handling in EmSjLj to a function (NFC) 2021-08-25 15:45:38 -07:00
WinEHPrepare.cpp [Local] Do not introduce a new `llvm.trap` before `unreachable` 2021-07-26 23:33:36 -05:00
XRayInstrumentation.cpp [xray] Honor xray-never function-instrument attribute 2021-01-19 18:47:09 -05:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

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With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

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The ocaml frametable structure supports liveness information. It would be good
to support it.

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The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

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It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side
effects).  Once this is in place, it would be even better to have tblgen
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStacks analysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

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Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.