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AArch64
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[GISel]: Verify COPIES involving generic registers.
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2018-02-09 01:27:23 +00:00 |
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AMDGPU
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AMDGPU: Minor cleanups
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2018-02-08 22:46:38 +00:00 |
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ARC
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…
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ARM
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[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
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2018-02-09 00:10:31 +00:00 |
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AVR
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[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
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2018-02-09 00:10:31 +00:00 |
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BPF
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bpf: Improve expanding logic in LowerSELECT_CC
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2018-02-08 04:37:49 +00:00 |
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Generic
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[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
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2018-02-09 00:10:31 +00:00 |
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Hexagon
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[CodeGen] Unify the syntax of MBB liveins in MIR and -debug output
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2018-02-09 01:14:44 +00:00 |
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Inputs
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…
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Lanai
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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MIR
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[GISel]: Verify COPIES involving generic registers.
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2018-02-09 01:27:23 +00:00 |
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MSP430
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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Mips
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Revert accidental changes that snuck in r324584
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2018-02-08 09:31:48 +00:00 |
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NVPTX
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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Nios2
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[Nios2] Arithmetic instructions for R1 and R2 ISA.
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2018-01-09 11:15:08 +00:00 |
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PowerPC
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[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."
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2018-02-07 09:58:55 +00:00 |
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RISCV
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[RISCV] Update two RISCV codegen tests after rL323991
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2018-02-03 13:02:30 +00:00 |
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SPARC
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[MachineCopyPropagation] Extend pass to do COPY source forwarding
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2018-02-01 18:54:01 +00:00 |
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SystemZ
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[SelectionDAG] Consider endianness in scalarizeVectorStore().
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2018-02-02 08:48:02 +00:00 |
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Thumb
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[LivePhysRegs] Fix handling of return instructions.
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2018-02-06 23:00:17 +00:00 |
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Thumb2
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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WebAssembly
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[WebAssembly] Fix test expectations after r324274
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2018-02-06 01:21:17 +00:00 |
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WinCFGuard
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Reland "Emit Function IDs table for Control Flow Guard"
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2018-01-09 23:49:30 +00:00 |
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WinEH
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…
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X86
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[X86] Add 512-bit shuffle test cases for concatenating 128/256-bits with zeros in the upper portion.
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2018-02-09 05:54:31 +00:00 |
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XCore
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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