forked from OSchip/llvm-project
71 lines
1.8 KiB
LLVM
71 lines
1.8 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Uses llvm.amdgcn.break
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; OPT-LABEL: @break_loop(
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; OPT: bb1:
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; OPT: call i64 @llvm.amdgcn.break(i64
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT: load volatile
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; OPT: xor i1 %cmp1
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; OPT: call i64 @llvm.amdgcn.if.break(
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; OPT: br label %Flow
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; OPT: Flow:
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; OPT: call i1 @llvm.amdgcn.loop(i64
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; OPT: br i1 %{{[0-9]+}}, label %bb9, label %bb1
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; OPT: bb9:
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; OPT: call void @llvm.amdgcn.end.cf(i64
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; TODO: Can remove exec fixes in return block
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; GCN-LABEL: {{^}}break_loop:
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; GCN: s_mov_b64 [[INITMASK:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: [[LOOP_ENTRY:BB[0-9]+_[0-9]+]]: ; %bb1
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; GCN: s_or_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[INITMASK]]
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; GCN: s_cmp_gt_i32 s{{[0-9]+}}, -1
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; GCN-NEXT: s_cbranch_scc1 [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: ; BB#2: ; %bb4
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; GCN: buffer_load_dword
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; GCN: v_cmp_ge_i32_e32 vcc,
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; GCN: s_or_b64 [[MASK]], vcc, [[INITMASK]]
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; GCN: [[FLOW]]:
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; GCN: s_mov_b64 [[INITMASK]], [[MASK]]
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; GCN: s_andn2_b64 exec, exec, [[MASK]]
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; GCN-NEXT: s_cbranch_execnz [[LOOP_ENTRY]]
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; GCN: ; BB#4: ; %bb9
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; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
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; GCN-NEXT: s_endpgm
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define void @break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %bb9
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bb4:
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load
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br i1 %cmp1, label %bb1, label %bb9
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bb9:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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