forked from OSchip/llvm-project
116 lines
4.2 KiB
C++
116 lines
4.2 KiB
C++
//===-- PIC16ISelLowering.h - PIC16 DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PIC16 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PIC16ISELLOWERING_H
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#define PIC16ISELLOWERING_H
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#include "PIC16.h"
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#include "PIC16Subtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace PIC16ISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Lo, // Low 8-bits of GlobalAddress.
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Hi, // High 8-bits of GlobalAddress.
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PIC16Load,
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PIC16Store,
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Banksel,
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MTLO,
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MTHI,
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BCF,
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LSLF, // PIC16 Logical shift left
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LRLF, // PIC16 Logical shift right
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RLF, // Rotate left through carry
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RRF, // Rotate right through carry
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Dummy
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};
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// Keep track of different address spaces.
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enum AddressSpace {
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RAM_SPACE = 0, // RAM address space
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ROM_SPACE = 1 // ROM address space number is 1
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class PIC16TargetLowering : public TargetLowering {
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public:
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explicit PIC16TargetLowering(PIC16TargetMachine &TM);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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SDValue LowerADDE(SDValue Op, SelectionDAG &DAG);
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SDValue LowerADDC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSUBE(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSUBC(SDValue Op, SelectionDAG &DAG);
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SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandStore(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandLoad(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandAdd(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandShift(SDNode *N, SelectionDAG &DAG);
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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private:
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// If the Node is a BUILD_PAIR representing representing an Address
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// then this function will return true
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bool isDirectAddress(const SDValue &Op);
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// If the Node is a DirectAddress in ROM_SPACE then this
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// function will return true
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bool isRomAddress(const SDValue &Op);
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// To extract chain value from the SDValue Nodes
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// This function will help to maintain the chain extracting
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// code at one place. In case of any change in future it will
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// help maintain the code
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SDValue getChain(SDValue &Op);
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// Extract the Lo and Hi component of Op.
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void GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo,
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SDValue &Hi);
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// Load pointer can be a direct or indirect address. In PIC16 direct
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// addresses need Banksel and Indirect addresses need to be loaded to
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// FSR first. Handle address specific cases here.
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void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
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SDValue &NewPtr, unsigned &Offset);
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// We can not have both operands of a binary operation in W.
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// This function is used to put one operand on stack and generate a load.
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SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG);
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/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const PIC16Subtarget *Subtarget;
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};
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} // namespace llvm
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#endif // PIC16ISELLOWERING_H
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