forked from OSchip/llvm-project
267 lines
9.0 KiB
TableGen
267 lines
9.0 KiB
TableGen
//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V3 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
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def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// J +
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//===----------------------------------------------------------------------===//
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// Call subroutine.
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let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
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isExtended = 0, isExtendable = 1, opExtendable = 0,
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isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
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class T_Call<string ExtStr>
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: JInst<(outs), (ins calltarget:$dst),
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"call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
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let BaseOpcode = "call";
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bits<24> dst;
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let IClass = 0b0101;
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let Inst{27-25} = 0b101;
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let Inst{24-16,13-1} = dst{23-2};
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let Inst{0} = 0b0;
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}
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let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
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isExtended = 0, isExtendable = 1, opExtendable = 1,
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isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
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class T_CallPred<bit IfTrue, string ExtStr>
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: JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
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CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
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[], "", J_tc_2early_SLOT23> {
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let BaseOpcode = "call";
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let isPredicatedFalse = !if(IfTrue,0,1);
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bits<2> Pu;
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bits<17> dst;
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let IClass = 0b0101;
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let Inst{27-24} = 0b1101;
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let Inst{23-22,20-16,13,7-1} = dst{16-2};
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let Inst{21} = !if(IfTrue,0,1);
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let Inst{11} = 0b0;
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let Inst{9-8} = Pu;
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}
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multiclass T_Calls<string ExtStr> {
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def NAME : T_Call<ExtStr>;
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def t : T_CallPred<1, ExtStr>;
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def f : T_CallPred<0, ExtStr>;
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}
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defm J2_call: T_Calls<"">, PredRel;
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let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
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def CALLv3nr : T_Call<"">, PredRel;
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//===----------------------------------------------------------------------===//
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// J -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// JR +
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//===----------------------------------------------------------------------===//
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// Call subroutine from register.
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let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
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def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
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}
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//===----------------------------------------------------------------------===//
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// JR -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU64/ALU +
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//===----------------------------------------------------------------------===//
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let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
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def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
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class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
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: T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
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def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
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def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
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let hasSideEffects = 0, isAsmParserOnly = 1 in
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def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
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(ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
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[(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
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(i64 DoubleRegs:$Rt))))],
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"", ALU64_tc_1_SLOT23>;
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let hasSideEffects = 0 in
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class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
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: ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
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"$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
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#"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
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bits<5> Rd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1101;
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let Inst{27-23} = 0b00111;
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let Inst{22-21} = !if(isMax, 0b10, 0b01);
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let Inst{20-16} = !if(isMax, Rt, Rs);
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let Inst{12-8} = !if(isMax, Rs, Rt);
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let Inst{7} = 0b1;
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let Inst{6} = !if(isMax, 0b0, 0b1);
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let Inst{5} = isUnsigned;
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let Inst{4-0} = Rd;
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}
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def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
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def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
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def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
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def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
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multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
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defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
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}
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let AddedComplexity = 200 in {
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defm: MinMax_pats_p<setge, A2_maxp, A2_minp>;
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defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
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defm: MinMax_pats_p<setle, A2_minp, A2_maxp>;
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defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
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defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
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defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
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defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
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defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
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}
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//===----------------------------------------------------------------------===//
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// ALU64/ALU -
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//===----------------------------------------------------------------------===//
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//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>;
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//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>;
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//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>;
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//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
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//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
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// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
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// Map call instruction
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def : Pat<(callv3 (i32 IntRegs:$dst)),
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(J2_callr (i32 IntRegs:$dst))>;
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def : Pat<(callv3 tglobaladdr:$dst),
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(J2_call tglobaladdr:$dst)>;
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def : Pat<(callv3 texternalsym:$dst),
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(J2_call texternalsym:$dst)>;
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def : Pat<(callv3 tglobaltlsaddr:$dst),
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(J2_call tglobaltlsaddr:$dst)>;
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def : Pat<(callv3nr (i32 IntRegs:$dst)),
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(CALLRv3nr (i32 IntRegs:$dst))>;
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def : Pat<(callv3nr tglobaladdr:$dst),
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(CALLv3nr tglobaladdr:$dst)>;
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def : Pat<(callv3nr texternalsym:$dst),
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(CALLv3nr texternalsym:$dst)>;
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//===----------------------------------------------------------------------===//
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// :raw form of vrcmpys:hi/lo insns
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//===----------------------------------------------------------------------===//
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// Vector reduce complex multiply by scalar.
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let Defs = [USR_OVF], hasSideEffects = 0 in
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class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
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MInst<(outs DoubleRegs:$Rdd),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1000;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{7-5} = 0b100;
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let Inst{4-0} = Rdd;
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}
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def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
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def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
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// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
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let hasSideEffects = 0, isAsmParserOnly = 1 in
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def M2_vrcmpys_s1
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: MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
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// Vector reduce complex multiply by scalar with accumulation.
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let Defs = [USR_OVF], hasSideEffects = 0 in
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class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
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MInst <(outs DoubleRegs:$Rxx),
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(ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
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"$Rxx = $_src_"> {
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bits<5> Rxx;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1110;
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let Inst{27-24} = 0b1010;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{7-5} = 0b100;
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let Inst{4-0} = Rxx;
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}
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def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
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def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
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// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
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let isAsmParserOnly = 1 in
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def M2_vrcmpys_acc_s1
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: MInst <(outs DoubleRegs:$dst),
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(ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
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"$dst += vrcmpys($src1, $src2):<<1:sat", [],
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"$dst2 = $dst">;
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def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
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def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
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// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
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let isAsmParserOnly = 1 in
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def M2_vrcmpys_s1rp
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: MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
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"$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
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// S2_cabacdecbin: Cabac decode bin.
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let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
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def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;
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