forked from OSchip/llvm-project
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector divide instructions on Power10.
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; This includes the low order and extended versions of vector divide,
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; that operate on signed and unsigned words and doublewords.
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define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivud v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <2 x i64> @test_vdivsd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <4 x i32> @test_vdivuw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivuw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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define <4 x i32> @test_vdivsw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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