forked from OSchip/llvm-project
123 lines
3.3 KiB
LLVM
123 lines
3.3 KiB
LLVM
; XFAIL: *
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i16 0, align 2
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define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iness:
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; CHECK: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iness_sext:
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; CHECK: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_iness_z(i16 signext %a) {
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; CHECK-LABEL: test_iness_z:
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; CHECK: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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}
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define signext i32 @test_iness_sext_z(i16 signext %a) {
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; CHECK-LABEL: test_iness_sext_z:
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; CHECK: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_iness_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iness_store:
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; CHECK: xor r3, r3, r4
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: test_iness_sext_store:
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; CHECK: xor r3, r3, r4
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: neg r3, r3
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; CHECK: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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define void @test_iness_z_store(i16 signext %a) {
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; CHECK-LABEL: test_iness_z_store:
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv2 = zext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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define void @test_iness_sext_z_store(i16 signext %a) {
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; CHECK-LABEL: test_iness_sext_z_store:
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; CHECK: cntlzw r3, r3
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; CHECK: srwi r3, r3, 5
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; CHECK: xori r3, r3, 1
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; CHECK: neg r3, r3
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; CHECK: sth r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i16 %a, 0
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%conv2 = sext i1 %cmp to i16
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store i16 %conv2, i16* @glob, align 2
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ret void
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}
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