forked from OSchip/llvm-project
203 lines
6.8 KiB
LLVM
203 lines
6.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}system_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @system_unordered(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out unordered, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}system_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @system_monotonic(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out monotonic, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}system_release
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @system_release(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out release, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}system_seq_cst
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @system_seq_cst(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @singlethread_unordered(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") unordered, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @singlethread_monotonic(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") monotonic, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_release
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @singlethread_release(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") release, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @singlethread_seq_cst(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}agent_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @agent_unordered(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") unordered, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}agent_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @agent_monotonic(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") monotonic, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}agent_release
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @agent_release(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") release, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}agent_seq_cst
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @agent_seq_cst(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @workgroup_unordered(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") unordered, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @workgroup_monotonic(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") monotonic, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_release
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @workgroup_release(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") release, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @workgroup_seq_cst(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @wavefront_unordered(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") unordered, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @wavefront_monotonic(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") monotonic, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_release
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @wavefront_release(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") release, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @wavefront_seq_cst(
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i32 %in, i32 addrspace(4)* %out) {
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entry:
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store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") seq_cst, align 4
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ret void
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}
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