llvm-project/llvm/test
Clement Courbet 07c9ec6f2e [X86][Sched] Add InstRW for CLC on Intel after SNB.
Summary:
After SNB, Intel CPUs can rename CF independently of other EFLAGS,
so the renamer can zero it for free. Note that STC still consumes resources.

To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC`

On SNB:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        sandybridge
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.0014, debug_string: SBPort0 }
  - { key: '4', value: 0.0013, debug_string: SBPort1 }
  - { key: '5', value: 0.0003, debug_string: SBPort4 }
  - { key: '6', value: 0.0029, debug_string: SBPort5 }
  - { key: '10', value: 0.0003, debug_string: SBPort23 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...
```

On HSW:
```
---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.001, debug_string: HWPort0 }
  - { key: '4', value: 0.0009, debug_string: HWPort1 }
  - { key: '5', value: 0.0004, debug_string: HWPort2 }
  - { key: '6', value: 0.0006, debug_string: HWPort3 }
  - { key: '7', value: 0.0002, debug_string: HWPort4 }
  - { key: '8', value: 0.0012, debug_string: HWPort5 }
  - { key: '9', value: 0.0022, debug_string: HWPort6 }
  - { key: '10', value: 0.0001, debug_string: HWPort7 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...

```

Reviewers: craig.topper, RKSimon

Subscribers: gchatelet, llvm-commits

Differential Revision: https://reviews.llvm.org/D47362

llvm-svn: 333392
2018-05-29 06:19:39 +00:00
..
Analysis Fix aliasing of launder.invariant.group 2018-05-23 09:16:44 +00:00
Assembler [ThinLTO] Fix a few more test match issues 2018-05-26 03:50:29 +00:00
Bindings [LLVM-C] [OCaml] Remove LLVMAddBBVectorizePass 2018-05-28 16:58:10 +00:00
Bitcode [ThinLTO] Fix a few more test match issues 2018-05-26 03:50:29 +00:00
BugPoint
CodeGen [X86][Sched] Add InstRW for CLC on Intel after SNB. 2018-05-29 06:19:39 +00:00
DebugInfo [Debugify] Set a DI version module flag for llc compatibility 2018-05-24 23:00:23 +00:00
Examples
ExecutionEngine Add handling for GlobalAliases in ExecutionEngine::getConstantValue. 2018-05-24 19:07:34 +00:00
Feature Restore the LoopInstSimplify pass, reverting r327329 that removed it. 2018-05-25 01:32:36 +00:00
FileCheck
Instrumentation [msan] Don't check divisor shadow in fdiv. 2018-05-18 20:19:53 +00:00
Integer
JitListener [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
LTO [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Linker [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
MC [PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores 2018-05-28 15:27:58 +00:00
Object [WebAsembly] Update default triple in test files to wasm32-unknown-unkown. 2018-05-10 17:49:11 +00:00
ObjectYAML Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes." 2018-05-17 22:55:15 +00:00
Other Revert r333268: [IPSCCP] Use PredicateInfo to propagate facts from... 2018-05-25 23:32:02 +00:00
SafepointIRVerifier SafepointIRVerifier is made unreachable block tolerant 2018-05-23 05:54:55 +00:00
SymbolRewriter
TableGen [GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9 2018-05-23 23:58:10 +00:00
ThinLTO/X86 [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Transforms [AMDGPU] Re-enabled 128bit wide-vector generation for local addr space by default. 2018-05-28 18:15:11 +00:00
Unit
Verifier [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
YAMLParser
tools [X86][Sched] Add InstRW for CLC on Intel after SNB. 2018-05-29 06:19:39 +00:00
.clang-format
CMakeLists.txt [tools] Add missing test dependency 2018-05-07 22:00:59 +00:00
TestRunner.sh
lit.cfg.py [tools] Adjust the lit config for llvm-strip 2018-05-07 21:07:01 +00:00
lit.site.cfg.py.in Remove 'abi-breaking-checks' lit feature. 2018-05-09 12:39:39 +00:00