llvm-project/mlir
River Riddle c89dff5855 [mlir][NFC] Split the non-templated bits out of IROperand into a base class
This removes the need to define the derived Operand class before the derived
Value class. The major benefit of this refactoring is that we no longer need
the OpaqueValue class, as OpOperand can now be defined after Value. As part of
this refactoring the BlockOperand and OpOperand classes are moved out of
UseDefLists.h and to more suitable locations in BlockSupport and Value. After
this change, UseDefLists.h is almost entirely composed of generic use def utilities.

Differential Revision: https://reviews.llvm.org/D103353
2021-06-02 12:48:37 -07:00
..
cmake/modules [MLIR] Make MLIR cmake variable names consistent 2021-05-24 08:43:10 +05:30
docs [mlir] Add support for filtering patterns based on debug names and labels 2021-06-02 12:05:25 -07:00
examples Add a helper function to convert LogicalResult to int for return from main 2021-05-19 00:12:39 +00:00
include [mlir][NFC] Split the non-templated bits out of IROperand into a base class 2021-06-02 12:48:37 -07:00
lib [mlir][NFC] Split the non-templated bits out of IROperand into a base class 2021-06-02 12:48:37 -07:00
python [mlir][python] Provide "all passes" registration module in Python 2021-05-26 15:14:57 -07:00
test [mlir] Resolve TODO and use the pass argument instead of the TypeID for registration 2021-06-02 12:17:36 -07:00
tools [mlir-reduce] Reducer refactor. 2021-06-02 07:45:00 +08:00
unittests [mlir][spirv] NFC: Replace OwningSPIRVModuleRef with OwningOpRef 2021-05-06 17:17:44 -04:00
utils [mlir] Add a vscode language extension for MLIR 2021-04-21 14:44:37 -07:00
.clang-format
.clang-tidy Fix MLIR clang-tidy: when tweaking it does not inherit from the parent 2020-03-07 17:44:21 +00:00
CMakeLists.txt [MLIR] Drop old cmake var names 2021-05-24 15:30:01 +05:30
LICENSE.TXT Add the Apache2 with LLVM exceptions license to MLIR 2019-12-24 00:58:06 -08:00
README.md mlir README.md: Fix the syntax 2019-12-24 13:31:07 +01:00

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.