llvm-project/llvm/test/CodeGen/Mips/msa
Jay Foad 719bac55df [MIRParser] Diagnose too large align values in MachineMemOperands
When parsing MachineMemOperands, MIRParser treated the "align" keyword
the same as "basealign". Really "basealign" should specify the
alignment of the MachinePointerInfo base value, and "align" should
specify the alignment of that base value plus the offset.

This worked OK when the specified alignment was no larger than the
alignment of the offset, but in cases like this it just caused
confusion:

    STW killed %18, 4, %stack.1.ap2.i.i :: (store (s32) into %stack.1.ap2.i.i + 4, align 8)

MIRPrinter would never have printed this, with an offset of 4 but an
align of 8, so it must have been written by hand. MIRParser would
interpret "align 8" as "basealign 8", but I think it is better to give
an error and force the user to write "basealign 8" if that is what they
really meant.

Differential Revision: https://reviews.llvm.org/D120400

Change-Id: I7eeeefc55c2df3554ba8d89f8809a2f45ada32d8
2022-02-24 15:32:08 +00:00
..
2r.ll
2r_vector_scalar.ll
2rf.ll
2rf_exup.ll
2rf_float_int.ll
2rf_fq.ll
2rf_int_float.ll
2rf_tq.ll
3r-a.ll
3r-b.ll
3r-c.ll
3r-d.ll
3r-i.ll
3r-m.ll
3r-p.ll
3r-s.ll [FileCheck] Allow literal '['s before "[[var...]]" 2022-01-13 09:47:37 +00:00
3r-v.ll
3r_4r.ll
3r_4r_widen.ll
3r_splat.ll
3rf.ll
3rf_4rf.ll
3rf_4rf_q.ll
3rf_exdo.ll
3rf_float_int.ll
3rf_int_float.ll
3rf_q.ll
arithmetic.ll
arithmetic_float.ll
avoid_vector_shift_combines.ll
basic_operations.ll [MIPS][MSA] Regenerate basic operations test checks 2021-07-20 13:37:44 +01:00
basic_operations_float.ll [FileCheck] Allow literal '['s before "[[var...]]" 2022-01-13 09:47:37 +00:00
bit.ll
bitcast.ll
bitwise.ll [MIPS][MSA] Regenerate bitwise tests. NFCI. 2021-05-05 16:03:19 +01:00
bmzi_bmnzi.ll
cc_without_nan.ll
compare.ll
compare_float.ll
elm_copy.ll
elm_cxcmsa.ll
elm_insv.ll
elm_move.ll
elm_shift_slide.ll
emergency-spill.mir [MIRParser] Diagnose too large align values in MachineMemOperands 2022-02-24 15:32:08 +00:00
endian.ll
f16-llvm-ir.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
fexuprl.ll
frameindex.ll [MC][mips] Remove unused check prefixes. NFC 2020-11-13 14:31:13 +03:00
i5-a.ll
i5-b.ll [MIPS][MSA] Regenerate i5-b tests. NFCI. 2021-05-05 16:03:19 +01:00
i5-c.ll
i5-m.ll
i5-s.ll [MC][mips] Remove unused check prefixes. NFC 2020-11-13 14:31:13 +03:00
i5_ld_st.ll
i8.ll
i10.ll
immediates-bad.ll
immediates.ll [MIPS][MSA] Regenerate immediates tests. NFCI. 2021-05-05 16:03:19 +01:00
inline-asm.ll
ldr_str.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
llvm-stress-s449609655-simplified.ll
llvm-stress-s525530439.ll
llvm-stress-s997348632.ll
llvm-stress-s1704963983.ll
llvm-stress-s1935737938.ll
llvm-stress-s2090927243-simplified.ll
llvm-stress-s2501752154-simplified.ll
llvm-stress-s2704903805.ll
llvm-stress-s3861334421.ll
llvm-stress-s3926023935.ll
llvm-stress-s3997499501.ll
llvm-stress-sz1-s742806235.ll
msa-nooddspreg.ll
nori.b.ll
remat-ldi.ll
shift-dagcombine.ll
shift_constant_pool.ll
shift_no_and.ll
shuffle.ll
special.ll
spill.ll
vec.ll
vecs10.ll