forked from OSchip/llvm-project
43 lines
2.0 KiB
LLVM
43 lines
2.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; FIXME: Move this to sgpr-copy.ll when this is fixed on VI.
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; Make sure that when we split an smrd instruction in order to move it to
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; the VALU, we are also moving its users to the VALU.
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; GCN-LABEL: {{^}}split_smrd_add_worklist:
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; GCN: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
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define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(4)* inreg %arg) #0 {
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bb:
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%tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 96, i32 0)
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%tmp1 = bitcast float %tmp to i32
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br i1 undef, label %bb2, label %bb3
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bb2: ; preds = %bb
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unreachable
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bb3: ; preds = %bb
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%tmp4 = bitcast float %tmp to i32
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%tmp5 = add i32 %tmp4, 4
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i64 0, i64 %tmp6
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%tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0
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%tmp9 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float), <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp10 = extractelement <4 x float> %tmp9, i32 0
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%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
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ret void
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}
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", !2}
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!2 = !{!"tbaa root"}
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