llvm-project/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
---
name: spill_csr_sgpr_argument
tracksRegLiveness: true
liveins:
- { reg: '$sgpr50' }
body: |
bb.0:
liveins: $sgpr50
; CHECK-LABEL: name: spill_csr_sgpr_argument
; CHECK: liveins: $sgpr50, $vgpr0
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr50, 0, $vgpr0
; CHECK: S_NOP 0, implicit $sgpr50
; CHECK: $sgpr50 = S_MOV_B32 0
S_NOP 0, implicit $sgpr50
$sgpr50 = S_MOV_B32 0
...