forked from OSchip/llvm-project
472 lines
18 KiB
LLVM
472 lines
18 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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target datalayout = "A5"
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; FIXME: Why is this commuted only sometimes?
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
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%add0 = add i32 %arg0, %arg1
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ret i32 %add0
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 9
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN: buffer_store_dword [[K]], off, s[0:3], s32 offset:20
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; GCN: s_waitcnt vmcnt(0)
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 68
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define fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %arg0, i32 %arg1) #1 {
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%add0 = add i32 %arg0, %arg1
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ret i32 %add0
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32:
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define hidden fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_stack_object:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 68
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_callee_stack_object:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 136
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_callee_stack_object(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_unused_result:
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define fastcc void @sibling_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret void
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}
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; It doesn't make sense to do a tail from a kernel
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; GCN-LABEL: {{^}}kernel_call_i32_fastcc_i32_i32_unused_result:
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;define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret void
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_byval_i32:
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; GCN: s_waitcnt
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; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32{{$}}
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval(i32) align 4 %arg1) #1 {
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%arg1.load = load i32, i32 addrspace(5)* %arg1, align 4
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%add0 = add i32 %arg0, %arg1.load
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ret i32 %add0
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}
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; Tail call disallowed with byval in parent.
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32_byval_parent:
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; GCN-NOT: v_writelane_b32 v{{[0-9]+}}, s32
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32{{$}}
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; GCN: s_swappc_b64
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; GCN-NOT: v_readlane_b32 s32
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval(i32) %b.byval, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) %b.byval)
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ret i32 %ret
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}
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; Tail call disallowed with byval in parent, not callee. The stack
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; usage of incoming arguments must be <= the outgoing stack
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; arguments.
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32:
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; GCN-NOT: v0
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; GCN-NOT: s32
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; GCN: buffer_load_dword v1, off, s[0:3], 0 offset:16
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; GCN: buffer_store_dword v1, off, s[0:3], s32{{$}}
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) inttoptr (i32 16 to i32 addrspace(5)*))
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32_a32i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32 offset:4{{$}}
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; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:8{{$}}
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_0]]
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; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_1]]
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GFX9: v_add3_u32 v0, v0, v3, v2
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %arg0, i32 %arg1, [32 x i32] %large) #1 {
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%val_firststack = extractvalue [32 x i32] %large, 30
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%val_laststack = extractvalue [32 x i32] %large, 31
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%add0 = add i32 %arg0, %arg1
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%add1 = add i32 %add0, %val_firststack
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%add2 = add i32 %add1, %val_laststack
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ret i32 %add2
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}
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; FIXME: Why load and store same location for stack args?
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32:
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; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:4
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; GCN-DAG: buffer_load_dword [[LOAD_2:v[0-9]+]], off, s[0:3], s32 offset:8
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; GCN-NOT: s32
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; GCN-DAG: buffer_store_dword [[LOAD_0]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[LOAD_1]], off, s[0:3], s32 offset:4
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; GCN-DAG: buffer_store_dword [[LOAD_2]], off, s[0:3], s32 offset:8
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; GCN-NOT: s32
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32_stack_object:
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:32
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32_stack_object(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; If the callee requires more stack argument space than the caller,
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; don't do a tail call.
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; TODO: Do we really need this restriction?
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; GCN-LABEL: {{^}}no_sibling_call_callee_more_stack_space:
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; GCN: s_swappc_b64
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; GCN: s_setpc_b64
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define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
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ret i32 %ret
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}
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; Have another non-tail in the function
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_other_call:
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; GCN: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
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; GCN-NEXT: buffer_store_dword [[CSRV:v[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec
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; GCN: v_writelane_b32 [[CSRV]], s33, 2
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; GCN-DAG: s_addk_i32 s32, 0x400
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; GCN-DAG: s_getpc_b64 s[4:5]
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; GCN-DAG: s_add_u32 s4, s4, i32_fastcc_i32_i32@gotpcrel32@lo+4
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; GCN-DAG: s_addc_u32 s5, s5, i32_fastcc_i32_i32@gotpcrel32@hi+12
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; GCN-DAG: v_writelane_b32 [[CSRV]], s30, 0
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; GCN-DAG: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
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; GCN-DAG: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
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; GCN-DAG: v_writelane_b32 [[CSRV]], s31, 1
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; GCN: s_swappc_b64
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; GCN-DAG: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
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; GCN-DAG: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
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; GCN: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, sibling_call_i32_fastcc_i32_i32@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, sibling_call_i32_fastcc_i32_i32@rel32@hi+12
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; GCN-DAG: v_readlane_b32 s30, [[CSRV]], 0
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; GCN-DAG: v_readlane_b32 s31, [[CSRV]], 1
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; GCN: s_addk_i32 s32, 0xfc00
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; GCN-NEXT: v_readlane_b32 s33,
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword [[CSRV]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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; GCN-NEXT: s_setpc_b64 s[4:5]
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%other.call = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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%ret = tail call fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %other.call)
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ret i32 %ret
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}
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; Have stack object in caller and stack passed arguments. SP should be
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; in same place at function exit.
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; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32:
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; GCN-NOT: s33
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; GCN: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
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; GCN-NOT: s33
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
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; GCN: s_setpc_b64 s[4:5]
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define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area:
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; GCN-NOT: s33
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:48
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; GCN-NOT: s33
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; GCN: s_setpc_b64 s[4:5]
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define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area(i32 %a, i32 %b, [36 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
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ret i32 %ret
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}
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@func_ptr_gv = external unnamed_addr addrspace(4) constant i32(i32, i32)*, align 4
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; Do support tail calls with a uniform, but unknown, callee.
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; GCN-LABEL: {{^}}indirect_uniform_sibling_call_i32_fastcc_i32_i32:
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; GCN: s_load_dwordx2 [[GV_ADDR:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_load_dwordx2 [[FUNC_PTR:s\[[0-9]+:[0-9]+\]]], [[GV_ADDR]]
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; GCN: s_setpc_b64 [[FUNC_PTR]]
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define hidden fastcc i32 @indirect_uniform_sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%func.ptr.load = load i32(i32, i32)*, i32(i32, i32)* addrspace(4)* @func_ptr_gv
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%ret = tail call fastcc i32 %func.ptr.load(i32 %a, i32 %b)
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ret i32 %ret
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}
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; We can't support a tail call to a divergent target. Use a waterfall
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; loop around a regular call
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; GCN-LABEL: {{^}}indirect_divergent_sibling_call_i32_fastcc_i32_i32:
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; GCN: v_readfirstlane_b32
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; GCN: v_readfirstlane_b32
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; GCN: s_and_saveexec_b64
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; GCN: s_swappc_b64
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; GCN: s_cbranch_execnz
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; GCN: s_setpc_b64
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define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(i32(i32, i32)* %func.ptr, i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%add = add i32 %b, %c
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%ret = tail call fastcc i32 %func.ptr(i32 %a, i32 %add)
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ret i32 %ret
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}
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declare hidden void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) align 16, [2 x i64] addrspace(5)* byval([2 x i64]))
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; GCN-LABEL: {{^}}sibling_call_fastcc_multi_byval:
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; GCN-DAG: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+:[0-9]+\]]]
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; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:160
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:164
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:168
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:172
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:16{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:20{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:24{{$}}
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; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:28{{$}}
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; GCN: s_setpc_b64 [[TARGET_ADDR]]
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define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
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entry:
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%alloca0 = alloca [3 x i32], align 16, addrspace(5)
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%alloca1 = alloca [2 x i64], align 8, addrspace(5)
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store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca0
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store [2 x i64] zeroinitializer, [2 x i64] addrspace(5)* %alloca1
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tail call fastcc void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) %alloca0, [2 x i64] addrspace(5)* byval([2 x i64]) %alloca1)
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ret void
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}
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declare hidden void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) align 16, [32 x i32], i32)
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; Callee has a byval and non-byval stack passed argument
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; GCN-LABEL: {{^}}sibling_call_byval_and_stack_passed:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:12{{$}}
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; GCN-DAG: buffer_store_dword v0, off, s[0:3], s32 offset:16
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; GCN: v_mov_b32_e32 v0, 0
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; GCN: v_mov_b32_e32 v30, 0
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; GCN: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+:[0-9]+\]]]
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64 [[TARGET_ADDR]]
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define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64 x i32]) #1 {
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entry:
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%alloca = alloca [3 x i32], align 16, addrspace(5)
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store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca
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tail call fastcc void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) %alloca, [32 x i32] zeroinitializer, i32 %stack.out.arg)
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ret void
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}
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declare hidden fastcc i64 @i64_fastcc_i64(i64 %arg0)
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; GCN-LABEL: {{^}}sibling_call_i64_fastcc_i64:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
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entry:
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%ret = tail call fastcc i64 @i64_fastcc_i64(i64 %a)
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ret i64 %ret
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}
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declare hidden fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %arg0)
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; GCN-LABEL: {{^}}sibling_call_p1i8_fastcc_p1i8:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i8 addrspace(1)* @sibling_call_p1i8_fastcc_p1i8(i8 addrspace(1)* %a) #1 {
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entry:
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%ret = tail call fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %a)
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ret i8 addrspace(1)* %ret
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}
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declare hidden fastcc i16 @i16_fastcc_i16(i16 %arg0)
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; GCN-LABEL: {{^}}sibling_call_i16_fastcc_i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
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entry:
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%ret = tail call fastcc i16 @i16_fastcc_i16(i16 %a)
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ret i16 %ret
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}
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declare hidden fastcc half @f16_fastcc_f16(half %arg0)
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; GCN-LABEL: {{^}}sibling_call_f16_fastcc_f16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
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entry:
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%ret = tail call fastcc half @f16_fastcc_f16(half %a)
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ret half %ret
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}
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declare hidden fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v3i16_fastcc_v3i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1 {
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entry:
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%ret = tail call fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %a)
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ret <3 x i16> %ret
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}
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declare hidden fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v4i16_fastcc_v4i16:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1 {
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entry:
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%ret = tail call fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %a)
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ret <4 x i16> %ret
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}
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declare hidden fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %arg0)
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; GCN-LABEL: {{^}}sibling_call_v2i64_fastcc_v2i64:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1 {
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entry:
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%ret = tail call fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %a)
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ret <2 x i64> %ret
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline }
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