forked from OSchip/llvm-project
23 lines
1.2 KiB
LLVM
23 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
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; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr:
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; GCN-DAG: v_lshlrev_b64 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]], 2, v[4:5]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43
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; GCN: v_add_co_u32 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
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; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
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; GCN: global_atomic_csub v{{[0-9]+}}, v[[[LO]]:[[HI]]], [[K]], off offset:512 glc
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; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[EXTRA_LO]]:[[EXTRA_HI]]]
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define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
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%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
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%cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
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%shl = shl i64 %cast, 2
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%castback = inttoptr i64 %shl to i32 addrspace(1)*
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%val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %castback, i32 43)
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store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
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ret i32 %val
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}
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declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
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attributes #0 = { argmemonly nounwind }
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