forked from OSchip/llvm-project
83 lines
3.1 KiB
LLVM
83 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Combine on select c, (load x), (load y) -> load (select c, x, y)
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; drops MachinePointerInfo, so it can't be relied on for correctness.
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; GCN-LABEL: {{^}}select_ptr_crash_i64_flat:
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2
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; GCN: s_cmp_eq_u32
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; GCN: v_cndmask_b32
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; GCN: v_cndmask_b32
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; GCN-NOT: load_dword
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; GCN: flat_load_dwordx2
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; GCN-NOT: load_dword
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; GCN: flat_store_dwordx2
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define amdgpu_kernel void @select_ptr_crash_i64_flat(i32 %tmp, [8 x i32], i64* %ptr0, [8 x i32], i64* %ptr1, [8 x i32], i64 addrspace(1)* %ptr2) {
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%tmp2 = icmp eq i32 %tmp, 0
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%tmp3 = load i64, i64* %ptr0, align 8
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%tmp4 = load i64, i64* %ptr1, align 8
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%tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
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store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
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ret void
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}
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; The transform currently doesn't happen for non-addrspace 0, but it
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; should.
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; GCN-LABEL: {{^}}select_ptr_crash_i64_global:
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
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; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
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; GCN: v_cndmask_b32
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; GCN: v_cndmask_b32
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; GCN: flat_store_dwordx2
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define amdgpu_kernel void @select_ptr_crash_i64_global(i32 %tmp, [8 x i32], i64 addrspace(1)* %ptr0, [8 x i32], i64 addrspace(1)* %ptr1, [8 x i32], i64 addrspace(1)* %ptr2) {
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%tmp2 = icmp eq i32 %tmp, 0
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%tmp3 = load i64, i64 addrspace(1)* %ptr0, align 8
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%tmp4 = load i64, i64 addrspace(1)* %ptr1, align 8
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%tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
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store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
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ret void
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}
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; GCN-LABEL: {{^}}select_ptr_crash_i64_local:
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; GCN: ds_read_b64
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; GCN: ds_read_b64
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; GCN: v_cndmask_b32
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; GCN: v_cndmask_b32
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; GCN: flat_store_dwordx2
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define amdgpu_kernel void @select_ptr_crash_i64_local(i32 %tmp, i64 addrspace(3)* %ptr0, i64 addrspace(3)* %ptr1, i64 addrspace(1)* %ptr2) {
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%tmp2 = icmp eq i32 %tmp, 0
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%tmp3 = load i64, i64 addrspace(3)* %ptr0, align 8
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%tmp4 = load i64, i64 addrspace(3)* %ptr1, align 8
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%tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
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store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
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ret void
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}
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; The transform will break addressing mode matching, so unclear it
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; would be good to do
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; GCN-LABEL: {{^}}select_ptr_crash_i64_local_offsets:
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; GCN: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:128
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; GCN: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:512
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; GCN: v_cndmask_b32
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; GCN: v_cndmask_b32
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define amdgpu_kernel void @select_ptr_crash_i64_local_offsets(i32 %tmp, i64 addrspace(3)* %ptr0, i64 addrspace(3)* %ptr1, i64 addrspace(1)* %ptr2) {
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%tmp2 = icmp eq i32 %tmp, 0
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%gep0 = getelementptr inbounds i64, i64 addrspace(3)* %ptr0, i64 16
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%gep1 = getelementptr inbounds i64, i64 addrspace(3)* %ptr1, i64 64
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%tmp3 = load i64, i64 addrspace(3)* %gep0, align 8
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%tmp4 = load i64, i64 addrspace(3)* %gep1, align 8
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%tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
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store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
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ret void
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}
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