forked from OSchip/llvm-project
73 lines
2.8 KiB
YAML
73 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
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# Initially %2 starts out with 2 subranges (one for sub0, and one for
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# the rest of the lanes). After %2 is split, after refineSubRanges the
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# newly created register has a different set of lane masks since the
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# copy bundle uses 2 different defs to cover the register. This was
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# fixed by doing refineSubRanges after all the COPYs being inserted.
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---
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name: subrange_for_this_mask_not_found
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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occupancy: 7
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body: |
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; CHECK-LABEL: name: subrange_for_this_mask_not_found
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: S_NOP 0, implicit [[DEF1]]
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; CHECK: S_NOP 0, implicit [[DEF1]]
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; CHECK: [[DEF2:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
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; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: undef %5.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
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; CHECK: internal %5.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31:av_1024_align2 = COPY [[COPY]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
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; CHECK: }
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; CHECK: %5.sub0:av_1024_align2 = IMPLICIT_DEF
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; CHECK: S_NOP 0, implicit %5.sub0
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; CHECK: bb.3:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: S_NOP 0, implicit %5
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; CHECK: bb.4:
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; CHECK: successors: %bb.3(0x40000000), %bb.5(0x40000000)
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; CHECK: [[DEF2:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
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; CHECK: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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; CHECK: bb.5:
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; CHECK: undef %3.sub0:vreg_1024_align2 = COPY [[DEF]]
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; CHECK: S_NOP 0, implicit %3
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vreg_1024_align2 = IMPLICIT_DEF
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%2:vreg_1024_align2 = COPY %1
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bb.1:
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S_NOP 0, implicit %1
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S_NOP 0, implicit %1
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%1:vreg_1024_align2 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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bb.3:
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%2.sub0:vreg_1024_align2 = IMPLICIT_DEF
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S_NOP 0, implicit %2.sub0
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bb.4:
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S_NOP 0, implicit %2
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bb.5:
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%2:vreg_1024_align2 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc
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bb.6:
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undef %4.sub0:vreg_1024_align2 = COPY %0
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S_NOP 0, implicit %4
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...
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