forked from OSchip/llvm-project
73 lines
2.4 KiB
YAML
73 lines
2.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: cttz_zero_undef_s32_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: cttz_zero_undef_s32_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
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; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: cttz_zero_undef_s32_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: cttz_zero_undef_s32_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
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; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: cttz_zero_undef_s64_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: cttz_zero_undef_s64_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
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; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: cttz_zero_undef_s64_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: cttz_zero_undef_s64_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[AMDGPU_FFBL_B32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32)
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; CHECK: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32
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; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[AMDGPU_FFBL_B32_1]], [[C]]
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; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[ADD]]
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; CHECK: S_ENDPGM 0, implicit [[UMIN]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
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S_ENDPGM 0, implicit %1
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...
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