forked from OSchip/llvm-project
262 lines
9.9 KiB
YAML
262 lines
9.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_fmed3_f32_known_nnan_ieee_true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_f32_known_nnan_ieee_true
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%8:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %8
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%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%9:vgpr(s32) = COPY %5(s32)
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%10:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %9(s32), %10(s32)
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$vgpr0 = COPY %4(s32)
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...
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---
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name: test_fmed3_f16_known_nnan_ieee_false
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_f16_known_nnan_ieee_false
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)
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; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
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%2:vgpr(s32) = COPY $vgpr0
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%0:vgpr(s16) = G_TRUNC %2(s32)
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%3:sgpr(s16) = G_FCONSTANT half 0xH4000
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%10:vgpr(s16) = COPY %3(s16)
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%4:vgpr(s16) = G_FMUL %0, %10
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%7:sgpr(s16) = G_FCONSTANT half 0xH3C00
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%6:sgpr(s16) = G_FCONSTANT half 0xH0000
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%11:vgpr(s16) = COPY %6(s16)
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%12:vgpr(s16) = COPY %7(s16)
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%5:vgpr(s16) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %4(s16), %11(s16), %12(s16)
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%9:vgpr(s32) = G_ANYEXT %5(s16)
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$vgpr0 = COPY %9(s32)
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...
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---
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name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01
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; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 1.000000e+01
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%8:vgpr(s32) = G_FCANONICALIZE %0
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%9:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMINNUM_IEEE %8, %9
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%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%10:vgpr(s32) = COPY %5(s32)
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%11:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %10(s32), %11(s32)
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$vgpr0 = COPY %4(s32)
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...
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---
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name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%8:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %8
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%6:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%9:vgpr(s32) = COPY %5(s32)
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%10:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %9(s32), %10(s32)
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$vgpr0 = COPY %4(s32)
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...
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# FixMe: add tests with attributes #3 = {"no-nans-fp-math"="true"}
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---
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name: test_fmed3_f32_maybe_NaN_ieee_false
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_f32_maybe_NaN_ieee_false
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FMUL]](s32), [[COPY2]](s32), [[COPY3]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%8:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %8
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%6:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%9:vgpr(s32) = COPY %5(s32)
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%10:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %9(s32), %10(s32)
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$vgpr0 = COPY %4(s32)
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...
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---
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name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: false
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01
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; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FMINNUM_IEEE]](s32), [[COPY2]](s32), [[COPY3]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 1.000000e+01
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%8:vgpr(s32) = G_FCANONICALIZE %0
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%9:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMINNUM_IEEE %8, %9
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%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%10:vgpr(s32) = COPY %5(s32)
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%11:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %10(s32), %11(s32)
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$vgpr0 = COPY %4(s32)
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...
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---
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name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FMUL]](s32), [[COPY2]](s32), [[COPY3]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%8:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %8
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%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%5:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%9:vgpr(s32) = COPY %5(s32)
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%10:vgpr(s32) = COPY %6(s32)
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %9(s32), %10(s32)
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$vgpr0 = COPY %4(s32)
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...
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