forked from OSchip/llvm-project
50 lines
1.6 KiB
YAML
50 lines
1.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: fminnum_f16_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: fminnum_f16_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK: %4:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; CHECK: S_ENDPGM 0, implicit %4
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FMINNUM %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fminnum_f16_v_fneg_v
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: fminnum_f16_v_fneg_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK: %5:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
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; CHECK: S_ENDPGM 0, implicit %5
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FNEG %3
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%5:vgpr(s16) = G_FMINNUM %2, %4
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S_ENDPGM 0, implicit %5
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...
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