forked from OSchip/llvm-project
299 lines
11 KiB
LLVM
299 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefix=GFX78 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=GFX78 %s
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define double @v_floor_f64_ieee(double %x) {
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; GFX6-LABEL: v_floor_f64_ieee:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e32 v[2:3], v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_ieee:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%result = call double @llvm.floor.f64(double %x)
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ret double %result
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}
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define double @v_floor_f64_ieee_nnan(double %x) {
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; GFX6-LABEL: v_floor_f64_ieee_nnan:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e32 v[2:3], v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_ieee_nnan:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%result = call nnan double @llvm.floor.f64(double %x)
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ret double %result
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}
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define double @v_floor_f64_ieee_fneg(double %x) {
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; GFX6-LABEL: v_floor_f64_ieee_fneg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e64 v[2:3], -v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_ieee_fneg:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], -v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%neg.x = fneg double %x
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%result = call double @llvm.floor.f64(double %neg.x)
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ret double %result
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}
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define double @v_floor_f64_nonieee(double %x) #1 {
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; GFX6-LABEL: v_floor_f64_nonieee:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e32 v[2:3], v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_nonieee:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%result = call double @llvm.floor.f64(double %x)
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ret double %result
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}
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define double @v_floor_f64_nonieee_nnan(double %x) #1 {
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; GFX6-LABEL: v_floor_f64_nonieee_nnan:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e32 v[2:3], v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_nonieee_nnan:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%result = call nnan double @llvm.floor.f64(double %x)
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ret double %result
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}
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define double @v_floor_f64_non_ieee_fneg(double %x) #1 {
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; GFX6-LABEL: v_floor_f64_non_ieee_fneg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e64 v[2:3], -v[0:1]
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], -v[0:1], -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_non_ieee_fneg:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], -v[0:1]
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%neg.x = fneg double %x
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%result = call double @llvm.floor.f64(double %neg.x)
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ret double %result
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}
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define double @v_floor_f64_fabs(double %x) {
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; GFX6-LABEL: v_floor_f64_fabs:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e64 v[2:3], |v[0:1]|
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], |v[0:1]|, -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_fabs:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], |v[0:1]|
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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; GFX7-LABEL: v_floor_f64_fabs:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_floor_f64_e64 v[0:1], |v[0:1]|
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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%abs.x = call double @llvm.fabs.f64(double %x)
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%result = call double @llvm.floor.f64(double %abs.x)
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ret double %result
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}
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define double @v_floor_f64_fneg_fabs(double %x) {
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; GFX6-LABEL: v_floor_f64_fneg_fabs:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX6-NEXT: v_fract_f64_e64 v[2:3], -|v[0:1]|
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; GFX6-NEXT: s_mov_b32 s4, -1
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; GFX6-NEXT: s_mov_b32 s5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], s[4:5]
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; GFX6-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1]
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], -|v[0:1]|, -v[2:3]
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; GFX6-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX78-LABEL: v_floor_f64_fneg_fabs:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], -|v[0:1]|
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; GFX78-NEXT: s_setpc_b64 s[30:31]
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%abs.x = call double @llvm.fabs.f64(double %x)
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%neg.abs.x = fneg double %abs.x
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%result = call double @llvm.floor.f64(double %neg.abs.x)
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ret double %result
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}
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define amdgpu_ps <2 x float> @s_floor_f64(double inreg %x) {
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; GFX6-LABEL: s_floor_f64:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: v_fract_f64_e32 v[0:1], s[2:3]
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; GFX6-NEXT: s_mov_b32 s0, -1
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; GFX6-NEXT: s_mov_b32 s1, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[0:1], v[0:1], s[0:1]
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; GFX6-NEXT: v_cmp_o_f64_e64 vcc, s[2:3], s[2:3]
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; GFX6-NEXT: v_mov_b32_e32 v2, s2
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; GFX6-NEXT: v_mov_b32_e32 v3, s3
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; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], s[2:3], -v[0:1]
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX78-LABEL: s_floor_f64:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: v_floor_f64_e32 v[0:1], s[2:3]
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; GFX78-NEXT: ; return to shader part epilog
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%result = call double @llvm.floor.f64(double %x)
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%cast = bitcast double %result to <2 x float>
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ret <2 x float> %cast
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}
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define amdgpu_ps <2 x float> @s_floor_f64_fneg(double inreg %x) {
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; GFX6-LABEL: s_floor_f64_fneg:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: v_fract_f64_e64 v[0:1], -s[2:3]
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; GFX6-NEXT: s_mov_b32 s0, -1
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; GFX6-NEXT: s_mov_b32 s1, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[0:1], v[0:1], s[0:1]
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; GFX6-NEXT: v_cmp_o_f64_e64 vcc, s[2:3], s[2:3]
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; GFX6-NEXT: v_mov_b32_e32 v2, s2
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; GFX6-NEXT: v_mov_b32_e32 v3, s3
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; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], -s[2:3], -v[0:1]
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX78-LABEL: s_floor_f64_fneg:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], -s[2:3]
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; GFX78-NEXT: ; return to shader part epilog
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%neg.x = fneg double %x
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%result = call double @llvm.floor.f64(double %neg.x)
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%cast = bitcast double %result to <2 x float>
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ret <2 x float> %cast
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}
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define amdgpu_ps <2 x float> @s_floor_f64_fabs(double inreg %x) {
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; GFX6-LABEL: s_floor_f64_fabs:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: v_fract_f64_e64 v[0:1], |s[2:3]|
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; GFX6-NEXT: s_mov_b32 s0, -1
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; GFX6-NEXT: s_mov_b32 s1, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[0:1], v[0:1], s[0:1]
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; GFX6-NEXT: v_cmp_o_f64_e64 vcc, s[2:3], s[2:3]
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; GFX6-NEXT: v_mov_b32_e32 v2, s2
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; GFX6-NEXT: v_mov_b32_e32 v3, s3
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; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], |s[2:3]|, -v[0:1]
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX78-LABEL: s_floor_f64_fabs:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], |s[2:3]|
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; GFX78-NEXT: ; return to shader part epilog
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%abs.x = call double @llvm.fabs.f64(double %x)
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%result = call double @llvm.floor.f64(double %abs.x)
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%cast = bitcast double %result to <2 x float>
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ret <2 x float> %cast
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}
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define amdgpu_ps <2 x float> @s_floor_f64_fneg_fabs(double inreg %x) {
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; GFX6-LABEL: s_floor_f64_fneg_fabs:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: v_fract_f64_e64 v[0:1], -|s[2:3]|
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; GFX6-NEXT: s_mov_b32 s0, -1
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; GFX6-NEXT: s_mov_b32 s1, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[0:1], v[0:1], s[0:1]
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; GFX6-NEXT: v_cmp_o_f64_e64 vcc, s[2:3], s[2:3]
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; GFX6-NEXT: v_mov_b32_e32 v2, s2
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; GFX6-NEXT: v_mov_b32_e32 v3, s3
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; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], -|s[2:3]|, -v[0:1]
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; GFX6-NEXT: ; return to shader part epilog
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;
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; GFX78-LABEL: s_floor_f64_fneg_fabs:
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; GFX78: ; %bb.0:
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; GFX78-NEXT: v_floor_f64_e64 v[0:1], -|s[2:3]|
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; GFX78-NEXT: ; return to shader part epilog
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%abs.x = call double @llvm.fabs.f64(double %x)
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%neg.abs.x = fneg double %abs.x
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%result = call double @llvm.floor.f64(double %neg.abs.x)
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%cast = bitcast double %result to <2 x float>
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ret <2 x float> %cast
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}
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declare double @llvm.floor.f64(double) #0
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declare double @llvm.fabs.f64(double) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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attributes #1 = { "amdgpu-ieee"="false" }
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