forked from OSchip/llvm-project
157 lines
4.8 KiB
YAML
157 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_const_const_1
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const_1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: $sgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = G_CONSTANT i32 255
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%1:_(s32) = G_CONSTANT i32 15
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%2:_(s32) = G_OR %0(s32), %1(s32)
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$sgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_const_const_2
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const_2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: $vgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = G_CONSTANT i32 15
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%1:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_OR %0(s32), %1(s32)
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$vgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_const_const_3
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const_3
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
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; CHECK: $vgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = G_CONSTANT i32 1431655765
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%1:_(s32) = G_CONSTANT i32 1145324612
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%2:_(s32) = G_OR %1(s32), %0(s32)
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$vgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_or_or
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_or_or
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
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; CHECK: $vgpr0 = COPY [[OR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_CONSTANT i32 15
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%3:_(s32) = G_OR %0, %1(s32)
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%4:_(s32) = G_OR %3, %2
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$vgpr0 = COPY %4(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_shl_xor_or
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: test_shl_xor_or
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
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; CHECK: $sgpr0 = COPY [[XOR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 -1
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%3:_(s32) = G_CONSTANT i32 31
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%4:_(s32) = G_SHL %0, %1(s32)
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%5:_(s32) = G_XOR %4(s32), %2(s32)
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%6:_(s32) = G_OR %5(s32), %3(s32)
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$sgpr0 = COPY %6(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_lshr_xor_or
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_lshr_xor_or
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
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; CHECK: $vgpr0 = COPY [[XOR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 -1
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%3:_(s32) = G_CONSTANT i32 4160749568
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%4:_(s32) = G_LSHR %0, %1(s32)
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%5:_(s32) = G_XOR %4(s32), %2(s32)
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%6:_(s32) = G_OR %5(s32), %3(s32)
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$vgpr0 = COPY %6(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_or_non_const
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: test_or_non_const
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
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; CHECK: $sgpr0 = COPY [[XOR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_CONSTANT i32 16
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%3:_(s32) = G_CONSTANT i32 -1
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%4:_(s32) = G_CONSTANT i32 4294901760
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%5:_(s32) = G_LSHR %0, %2(s32)
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%6:_(s32) = G_XOR %5, %3(s32)
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%7:_(s32) = G_AND %1, %4(s32)
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%8:_(s32) = G_OR %6, %7
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$sgpr0 = COPY %8(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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