| .. |
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add.v2i16.ll
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[AMDGPU] Switch PostRA sched to MachineSched
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2021-09-14 15:11:27 -04:00 |
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add_shl.ll
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[AMDGPU] Make some VOP3 insts commutable
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2021-04-28 13:59:08 -04:00 |
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amdgpu-irtranslator.ll
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…
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andn2.ll
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[AMDGPU] Switch PostRA sched to MachineSched
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2021-09-14 15:11:27 -04:00 |
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artifact-combiner-anyext.mir
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AMDGPU: Regenerate some mir test checks with -NEXT
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2021-12-18 10:46:15 -05:00 |
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artifact-combiner-asserts.ll
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GlobalISel: Fix assert on unmerge to different element of casted vector
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2022-01-19 10:13:31 -05:00 |
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artifact-combiner-build-vector.mir
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AMDGPU: Regenerate some mir test checks with -NEXT
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2021-12-18 10:46:15 -05:00 |
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artifact-combiner-concat-vectors.mir
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AMDGPU: Regenerate some mir test checks with -NEXT
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2021-12-18 10:46:15 -05:00 |
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artifact-combiner-cse-leaves-dead-cast.mir
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GlobalISel: Fix legalization error where CSE leaves behind dead defs
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2022-01-18 17:04:40 -05:00 |
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artifact-combiner-extract.mir
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[GlobalISel] Rework more/fewer elements for vectors
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2021-12-23 14:30:02 +01:00 |
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artifact-combiner-sext.mir
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AMDGPU: Regenerate some mir test checks with -NEXT
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2021-12-18 10:46:15 -05:00 |
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artifact-combiner-trunc.mir
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AMDGPU: Regenerate some mir test checks with -NEXT
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2021-12-18 10:46:15 -05:00 |
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artifact-combiner-unmerge-values.mir
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GlobalISel: Fix assert on unmerge to different element of casted vector
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2022-01-19 10:13:31 -05:00 |
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artifact-combiner-zext.mir
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[GlobalISel] Rework more/fewer elements for vectors
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2021-12-23 14:30:02 +01:00 |
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ashr.ll
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AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
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2022-01-17 10:04:41 -05:00 |
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assert-align.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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atomic_load_local.ll
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[AMDGPU] Add patterns for i8/i16 local atomic load/store
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2021-10-18 11:23:10 +02:00 |
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atomic_optimizations_mul_one.ll
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[AMDGPU] Do not generate ELF symbols for the local branch target labels
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2021-11-20 10:32:41 +05:30 |
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atomic_store_local.ll
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[AMDGPU] Add patterns for i8/i16 local atomic load/store
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2021-10-18 11:23:10 +02:00 |
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bool-legalization.ll
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[AMDGPU] Do not generate ELF symbols for the local branch target labels
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2021-11-20 10:32:41 +05:30 |
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bswap.ll
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[AArch64][GlobalISel] combine and + [la]sr => ubfx
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2021-10-18 10:33:01 -07:00 |
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buffer-schedule.ll
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[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
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2021-07-26 14:27:30 +01:00 |
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bug-legalization-artifact-combiner-dead-def.ll
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GlobalISel: Fix infinite loop in legalization artifact combiner
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2021-08-02 12:58:10 +02:00 |
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bug-legalization-artifact-combiner-dead-def.mir
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[GlobalISel] Rework more/fewer elements for vectors
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2021-12-23 14:30:02 +01:00 |
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call-outgoing-stack-args.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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clamp-fmed3-const-combine.ll
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AMDGPU/GlobalISel: Add clamp combine
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2021-12-03 12:49:39 +01:00 |
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clamp-minmax-const-combine.ll
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AMDGPU/GlobalISel: Add clamp combine
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2021-12-03 12:49:39 +01:00 |
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combine-add-nullptr.mir
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[GlobalISel] Avoid making G_PTR_ADD with nullptr
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2020-10-13 13:02:55 +02:00 |
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combine-add-to-ptradd.mir
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AMDGPU/GlobalISel: Regenerate base test checks
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2022-01-18 11:26:47 -05:00 |
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combine-amdgpu-cvt-f32-ubyte.mir
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…
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combine-ashr-narrow.mir
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…
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combine-ext-legalizer.mir
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[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
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2021-08-24 11:09:56 +02:00 |
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combine-fabs-fneg.mir
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[GlobalISel] Combine fabs(fneg(x)) to fabs(x)
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2021-10-05 13:43:39 +02:00 |
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combine-fcanonicalize.mir
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AMDGPU/GlobalISel: Do not fcanonicalize const splat padded with undef
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2021-12-03 12:49:38 +01:00 |
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combine-fma-add-ext-fma.ll
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[AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))
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2021-11-29 16:27:21 +01:00 |
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combine-fma-add-ext-mul.ll
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[AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
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2021-11-29 16:27:21 +01:00 |
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combine-fma-add-fma-mul.ll
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[AMDGPU] Use v_fma_f16 on GFX10
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2021-12-15 13:14:48 +00:00 |
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combine-fma-add-mul-post-legalize.mir
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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combine-fma-add-mul-pre-legalize.mir
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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combine-fma-add-mul.ll
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GlobalIsel: Fix fma combine when one of the operands comes from unmerge
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2022-01-12 17:47:25 +01:00 |
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combine-fma-sub-ext-mul.ll
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[AMDGPU][GlobalISel] Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))
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2021-11-29 16:27:22 +01:00 |
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combine-fma-sub-ext-neg-mul.ll
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[AMDGPU][GlobalISel] Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))
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2021-11-29 16:27:22 +01:00 |
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combine-fma-sub-mul.ll
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[AMDGPU][GlobalISel] Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
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2021-11-29 16:27:22 +01:00 |
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combine-fma-sub-neg-mul.ll
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[AMDGPU][GlobalISel] Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
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2021-11-29 16:27:22 +01:00 |
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combine-fma-unmerge-values.mir
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GlobalIsel: Fix fma combine when one of the operands comes from unmerge
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2022-01-12 17:47:25 +01:00 |
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combine-fold-binop-into-select.mir
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GlobalISel: Constant fold G_PTR_ADD
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2022-02-08 19:21:06 -05:00 |
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combine-foldable-fneg.mir
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[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine
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2022-02-11 12:09:40 +01:00 |
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combine-fsh.mir
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[AMDGPU][GlobalISel] Remove the post ':' part of vreg operands in fsh combine tests.
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2022-01-24 16:30:40 +05:30 |
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combine-itofp.mir
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[AMDGPU] Regenerate some MIR checks
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2022-01-20 12:41:40 +00:00 |
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combine-lshr-narrow.mir
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…
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combine-or-redundant.mir
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[GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x
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2020-11-10 11:32:13 +01:00 |
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combine-redundant-and.mir
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[GlobalISel] Implement computeKnownBits for G_SEXT_INREG
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2021-01-26 15:01:38 -08:00 |
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combine-redundant-neg.mir
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[GlobalISel] Combine for eliminating redundant operand negations
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2021-10-08 14:29:22 +02:00 |
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combine-rot.mir
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[AMDGPU][GlobalISel] Remove the post ':' part of vreg operands in fsh combine tests.
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2022-01-24 16:30:40 +05:30 |
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combine-rsq.ll
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Code quality: Combine V_RSQ
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2021-11-30 17:17:15 +01:00 |
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combine-rsq.mir
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Code quality: Combine V_RSQ
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2021-11-30 17:17:15 +01:00 |
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combine-sext-inreg.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-shift-imm-chain-illegal-types.mir
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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combine-shift-imm-chain-shlsat.mir
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[AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands
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2020-11-10 11:32:12 +01:00 |
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combine-shift-imm-chain.ll
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[AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands
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2020-11-10 11:32:12 +01:00 |
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combine-shift-of-shifted-logic-shlsat.mir
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[AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands
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2020-11-10 11:32:13 +01:00 |
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combine-shift-of-shifted-logic.ll
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[GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x
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2020-11-10 11:32:13 +01:00 |
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combine-shl-from-extend-narrow.postlegal.mir
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…
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combine-shl-from-extend-narrow.prelegal.mir
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…
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combine-shl-narrow.mir
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[GlobalISel] Add `X,Y<dead> = G_UNMERGE Z` -> X = G_TRUNC Z
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2020-09-14 17:27:23 -07:00 |
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combine-short-clamp.ll
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[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
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2021-04-01 14:21:00 +03:00 |
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combine-trunc-shl.mir
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GlobalISel: Fix truncating shift amount in trunc (shl) combine
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2020-09-23 09:07:50 -04:00 |
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combine-urem-pow-2.mir
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[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR
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2021-12-21 11:59:33 +00:00 |
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combine-zext-trunc.mir
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Reland [GlobalISel] Combine zext(trunc x) to x
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2021-03-05 11:05:37 +01:00 |
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combiner-crash.ll
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GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors
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2022-01-18 17:21:02 -05:00 |
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constant-bus-restriction.ll
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
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crash-stack-address-O0.ll
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GlobalISel: Always enable GISelKnownBits for InstructionSelect
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2022-01-12 18:57:24 -05:00 |
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cvt_f32_ubyte.ll
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AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
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2021-12-20 18:07:11 -05:00 |
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divergent-control-flow.ll
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[StructurizeCFG] Clean up some boolean not instructions
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2022-02-01 09:35:37 +00:00 |
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dropped_debug_info_assert.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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dummy-target.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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dynamic-alloca-divergent.ll
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…
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dynamic-alloca-uniform.ll
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AMDGPU: Mark prolog/epilog SCC defs as dead
|
2021-11-15 21:35:06 -05:00 |
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extractelement-stack-lower.ll
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[AMDGPU] Do not reserve any VGPR for SGPR spills
|
2022-01-11 22:14:59 -08:00 |
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extractelement.i8.ll
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[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
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extractelement.i16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
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extractelement.i128.ll
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[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
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extractelement.ll
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AMDGPU: Optimize out implicit kernarg argument allocation if unused
|
2021-12-04 10:38:25 -05:00 |
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fdiv.f16.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
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fdiv.f32.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
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2022-03-09 12:18:02 +05:30 |
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fdiv.f64.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
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flat-scratch-init.gfx.ll
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[AMDGPU] Make enable-flat-scratch a subtarget feature
|
2022-02-11 18:23:07 +01:00 |
|
flat-scratch-init.ll
|
[AMDGPU] flat scratch SVS addressing mode for gfx940
|
2022-03-14 15:23:36 -07:00 |
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flat-scratch.ll
|
[AMDGPU] flat scratch SVS addressing mode for gfx940
|
2022-03-14 15:23:36 -07:00 |
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floor.f64.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
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fma.ll
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[AMDGPU] Use v_fma_f16 on GFX10
|
2021-12-15 13:14:48 +00:00 |
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fmax_legacy.ll
|
Revert "[AMDGPU] Insert waitcnt after returning from call"
|
2020-09-23 17:16:39 +02:00 |
|
fmed3-min-max-const-combine.ll
|
AMDGPU/GlobalISel: Fix introducing f16 fmed3 for gfx8
|
2022-01-19 10:43:21 -05:00 |
|
fmed3.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
fmin_legacy.ll
|
Revert "[AMDGPU] Insert waitcnt after returning from call"
|
2020-09-23 17:16:39 +02:00 |
|
fmul.v2f16.ll
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[GlobalISel] Combine for eliminating redundant operand negations
|
2021-10-08 14:29:22 +02:00 |
|
fp-atomics-gfx940.ll
|
[AMDGPU] new gfx940 fp atomics
|
2022-03-07 12:32:02 -08:00 |
|
fp64-atomics-gfx90a.ll
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AMDGPU/GlobalISel: Stop handling llvm.amdgcn.buffer.atomic.fadd
|
2022-01-20 12:12:06 -05:00 |
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fpow.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
frem.ll
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
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fshl.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
fshr.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
function-returns.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
function-returns.v2i65.ll
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AMDGPU/GlobalISel: Add failing ABI lowering testcases
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2022-01-17 09:38:35 -05:00 |
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global-value.illegal.ll
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AMDGPU/GlobalISel: Explicitly set -global-isel-abort in failure tests
|
2022-01-20 12:56:53 -05:00 |
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global-value.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
hip.extern.shared.array.ll
|
…
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image-waterfall-loop-O0.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
implicit-kernarg-backend-usage-global-isel.ll
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AMDGPU: Use the implicit kernargs for code object version 5
|
2022-03-17 14:12:36 -07:00 |
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inline-asm-mismatched-size.ll
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[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
inline-asm.ll
|
Reapply "RegAllocFast: Rewrite and improve"
|
2020-09-30 10:35:25 -04:00 |
|
insertelement-stack-lower.ll
|
AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set
|
2021-10-22 16:23:50 -04:00 |
|
insertelement.i8.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
insertelement.i16.ll
|
GlobalISel: Constant fold G_PTR_ADD
|
2022-02-08 19:21:06 -05:00 |
|
insertelement.large.ll
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
insertelement.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
inst-select-abs.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-add.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-add.s16.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.class.mir
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GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
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inst-select-amdgcn.class.s16.mir
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GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
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inst-select-amdgcn.cos.mir
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…
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inst-select-amdgcn.cos.s16.mir
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…
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inst-select-amdgcn.cvt.pk.i16.mir
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…
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inst-select-amdgcn.cvt.pk.u16.mir
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…
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inst-select-amdgcn.cvt.pknorm.i16.mir
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…
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inst-select-amdgcn.cvt.pknorm.u16.mir
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…
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inst-select-amdgcn.cvt.pkrtz.mir
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…
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inst-select-amdgcn.ds.swizzle.mir
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…
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inst-select-amdgcn.exp.mir
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…
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inst-select-amdgcn.fmad.ftz.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fmed3.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fmed3.s16.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fract.mir
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…
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inst-select-amdgcn.fract.s16.mir
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…
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inst-select-amdgcn.groupstaticsize.mir
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…
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inst-select-amdgcn.ldexp.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.ldexp.s16.mir
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…
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inst-select-amdgcn.mbcnt.lo.mir
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…
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inst-select-amdgcn.mul.u24.mir
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…
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inst-select-amdgcn.mulhi.i24.mir
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[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
|
2021-10-26 18:53:07 +05:30 |
|
inst-select-amdgcn.mulhi.u24.mir
|
[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
|
2021-10-26 18:53:07 +05:30 |
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inst-select-amdgcn.rcp.legacy.mir
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…
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inst-select-amdgcn.rcp.mir
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…
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inst-select-amdgcn.rcp.s16.mir
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…
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inst-select-amdgcn.readfirstlane.mir
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…
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inst-select-amdgcn.reloc.constant.mir
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…
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inst-select-amdgcn.rsq.clamp.mir
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…
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inst-select-amdgcn.rsq.legacy.mir
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…
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inst-select-amdgcn.rsq.mir
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…
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inst-select-amdgcn.rsq.s16.mir
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…
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inst-select-amdgcn.s.barrier.mir
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…
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inst-select-amdgcn.s.sendmsg.mir
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…
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inst-select-amdgcn.sffbh.mir
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…
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inst-select-amdgcn.sin.mir
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…
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inst-select-amdgcn.sin.s16.mir
|
…
|
|
|
inst-select-amdgpu-atomic-cmpxchg-flat.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-amdgpu-atomic-cmpxchg-global.mir
|
[AMDGPU] Use COPY_TO_REGCLASS for buffer_atomic_cmpswap selection
|
2022-03-18 08:56:23 +05:30 |
|
inst-select-amdgpu-ffbh-u32.mir
|
…
|
|
|
inst-select-amdgpu-ffbl-b32.mir
|
[AMDGPU][GlobalISel] Add G_AMDGPU_FFBL_B32
|
2021-08-06 09:40:48 +01:00 |
|
inst-select-amdgpu-wave-address.mir
|
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
|
2022-01-19 10:13:31 -05:00 |
|
inst-select-and.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-anyext.mir
|
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
|
2022-01-24 10:16:51 +00:00 |
|
inst-select-ashr.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-ashr.s16.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-ashr.v2s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-atomic-cmpxchg-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomic-cmpxchg-region.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-add-flat.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-add-global.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-fadd-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-fadd-region.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-xchg-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-atomicrmw-xchg-region.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-bitcast.mir
|
…
|
|
|
inst-select-bitreverse.mir
|
[AMDGPU] Better codegen for i64 bitreverse
|
2021-02-26 15:51:36 +00:00 |
|
inst-select-br.mir
|
…
|
|
|
inst-select-brcond.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-bswap.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-build-vector-trunc.v2s16.mir
|
[AMDGPU][GlobalISel] Avoid selecting S_PACK with constants
|
2021-01-20 11:54:53 +01:00 |
|
inst-select-build-vector.mir
|
…
|
|
|
inst-select-concat-vectors.mir
|
…
|
|
|
inst-select-constant.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-copy.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-ctlz-zero-undef.mir
|
…
|
|
|
inst-select-ctpop.mir
|
…
|
|
|
inst-select-cttz-zero-undef.mir
|
…
|
|
|
inst-select-extract-vector-elt.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-extract.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
inst-select-fabs.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-fadd.s16.mir
|
…
|
|
|
inst-select-fadd.s32.mir
|
…
|
|
|
inst-select-fadd.s64.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-fcanonicalize.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-fceil.mir
|
…
|
|
|
inst-select-fceil.s16.mir
|
…
|
|
|
inst-select-fcmp.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-fcmp.s16.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-fconstant.mir
|
…
|
|
|
inst-select-fexp2.mir
|
…
|
|
|
inst-select-ffloor.s16.mir
|
…
|
|
|
inst-select-ffloor.s32.mir
|
…
|
|
|
inst-select-ffloor.s64.mir
|
…
|
|
|
inst-select-fma.s32.mir
|
[AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used
|
2021-09-21 11:57:45 +01:00 |
|
inst-select-fmad.s32.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-fmaxnum-ieee.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fmaxnum-ieee.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fmaxnum-ieee.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fmaxnum.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fmaxnum.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fmaxnum.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fminnum-ieee.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fminnum-ieee.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fminnum-ieee.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fminnum.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fminnum.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fminnum.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fmul.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fmul.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fneg.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-fptosi.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-fptoui.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-fract.f64.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
inst-select-frame-index.mir
|
…
|
|
|
inst-select-freeze.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-frint.mir
|
…
|
|
|
inst-select-frint.s16.mir
|
…
|
|
|
inst-select-fshr.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-icmp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-icmp.s16.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-icmp.s64.mir
|
…
|
|
|
inst-select-implicit-def.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-insert-vector-elt.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-insert.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
inst-select-intrinsic-trunc.mir
|
…
|
|
|
inst-select-intrinsic-trunc.s16.mir
|
…
|
|
|
inst-select-inttoptr.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-atomic-flat.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-load-atomic-global.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-atomic-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-load-constant.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-load-flat.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-load-global-saddr.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-load-global.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-load-global.s96.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-load-local-128.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-load-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-load-private.mir
|
GlobalISel: Always enable GISelKnownBits for InstructionSelect
|
2022-01-12 18:57:24 -05:00 |
|
inst-select-load-smrd.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-lshr.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-lshr.s16.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-lshr.v2s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-merge-values.mir
|
…
|
|
|
inst-select-mul.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-or.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-pattern-add3.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-and-or.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-or3.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-smed3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-pattern-smed3.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-umed3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-pattern-umed3.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-xor3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-phi.mir
|
…
|
|
|
inst-select-ptr-add.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-ptrmask.mir
|
AMDGPU/GlobalISel: Try to use s_and_b64 in ptrmask selection
|
2022-01-20 12:56:53 -05:00 |
|
inst-select-ptrtoint.mir
|
…
|
|
|
inst-select-returnaddress.mir
|
…
|
|
|
inst-select-sbfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
inst-select-scalar-packed.xfail.mir
|
…
|
|
|
inst-select-select.mir
|
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
|
2021-11-23 19:37:07 +03:00 |
|
inst-select-sext-inreg.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-sext.mir
|
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
|
2022-01-24 10:16:51 +00:00 |
|
inst-select-sextload-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-shl.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-shl.s16.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-shl.v2s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-shuffle-vector.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-sitofp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-smax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-smin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-smulh.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-store-atomic-flat.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-store-atomic-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-store-flat.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-store-global.mir
|
[AMDGPU] Make v8i16/v8f16 legal
|
2022-01-24 11:51:08 -08:00 |
|
inst-select-store-global.s96.mir
|
[AMDGPU] Remove unused GFX6 check lines
|
2022-01-27 10:48:32 +00:00 |
|
inst-select-store-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
inst-select-store-private.mir
|
[AMDGPU] Reenable some disabled RUN lines
|
2022-02-15 11:28:24 +00:00 |
|
inst-select-sub.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-trunc.mir
|
…
|
|
|
inst-select-trunc.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-uadde.gfx10.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-uadde.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-uaddo.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-ubfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
inst-select-uitofp.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-umax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-umin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-umulh.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-unmerge-values.mir
|
…
|
|
|
inst-select-usube.gfx10.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-usube.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-usubo.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-xor.mir
|
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
|
2021-10-30 07:20:45 -04:00 |
|
inst-select-zext.mir
|
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
|
2022-01-24 10:16:51 +00:00 |
|
inst-select-zextload-local.mir
|
AMDGPU/GlobalISel: Regenerate mir test checks
|
2022-01-12 13:44:06 -05:00 |
|
irtranslator-amdgcn-sendmsg.ll
|
AMDGPU: Regenerate more mir test checks with -NEXT
|
2021-12-18 11:38:30 -05:00 |
|
irtranslator-amdgpu_kernel-system-sgprs.ll
|
…
|
|
|
irtranslator-amdgpu_kernel.ll
|
[AMDGPU] Simplify AMDGPUAnnotateUniformValues::visitLoadInst
|
2022-02-03 16:27:48 +00:00 |
|
irtranslator-amdgpu_ps.ll
|
AMDGPU: Regenerate more mir test checks with -NEXT
|
2021-12-18 11:38:30 -05:00 |
|
irtranslator-amdgpu_vs.ll
|
AMDGPU: Regenerate more mir test checks with -NEXT
|
2021-12-18 11:38:30 -05:00 |
|
irtranslator-assert-align.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-atomicrmw.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-call-abi-attribute-hints.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-call-implicit-args.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-call-non-fixed.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-call-return-values.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-call-sret.ll
|
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
|
2022-01-19 10:13:31 -05:00 |
|
irtranslator-call.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-constant-fold-vector-op.ll
|
GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors
|
2022-01-18 17:21:02 -05:00 |
|
irtranslator-constantexpr.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-constrained-fp.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-fast-math-flags.ll
|
…
|
|
|
irtranslator-fence.ll
|
AMDGPU: Regenerate more mir test checks with -NEXT
|
2021-12-18 11:38:30 -05:00 |
|
irtranslator-fixed-function-abi-vgpr-args.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-function-args.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-function-args.v2i65.ll
|
AMDGPU/GlobalISel: Add failing ABI lowering testcases
|
2022-01-17 09:38:35 -05:00 |
|
irtranslator-getelementptr.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-indirect-call.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-inline-asm.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-memory-intrinsics.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-metadata.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-non-integral-address-spaces.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-ptrmask.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-readnone-intrinsic-callsite.ll
|
…
|
|
|
irtranslator-sat.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-sibling-call.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
irtranslator-struct-return-intrinsics.ll
|
AMDGPU: Regenerate more mir test checks with -NEXT
|
2021-12-18 11:38:30 -05:00 |
|
irtranslator-tail-call.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
lds-global-non-entry-func.ll
|
AMDGPU: Enable fixed function ABI by default
|
2021-12-04 10:49:18 -05:00 |
|
lds-global-value.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
lds-misaligned-bug.ll
|
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
|
2021-04-08 08:12:05 +05:30 |
|
lds-relocs.ll
|
[AMDGPU] Lower kernel LDS into a sorted structure
|
2021-05-25 11:29:29 -07:00 |
|
lds-size.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
lds-zero-initializer.ll
|
[AMDGPU] Legalize initialized LDS variables
|
2021-09-23 22:53:20 -04:00 |
|
legalize-add.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-addrspacecast.mir
|
AMDGPU: Avoid null check during addrspacecast lowering
|
2022-01-10 13:27:39 -05:00 |
|
legalize-amdgcn.if-invalid.mir
|
…
|
|
|
legalize-amdgcn.if.xfail.mir
|
…
|
|
|
legalize-amdgcn.rsq.clamp.mir
|
…
|
|
|
legalize-amdgcn.wavefrontsize.mir
|
…
|
|
|
legalize-and.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-anyext.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-ashr.mir
|
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
|
2022-01-17 10:04:41 -05:00 |
|
legalize-atomic-cmpxchg-with-success.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomic-cmpxchg.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-add.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-and.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-fadd-global.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-fadd-local.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-max.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-min.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-nand.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-or.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-sub.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-umax.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-umin.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-xchg-flat.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-xchg.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-atomicrmw-xor.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-bitcast.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-bitreverse.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-block-addr.mir
|
…
|
|
|
legalize-brcond.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-bswap.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-build-vector-trunc.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-build-vector.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-build-vector.s16.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-concat-vectors.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-constant.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-ctlz-zero-undef.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-ctlz.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-ctpop.mir
|
AMDGPU/GlobalISel: Fix legalize failure on i65 ctpop
|
2022-01-19 10:26:28 -05:00 |
|
legalize-cttz-zero-undef.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-cttz.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-extract-vector-elt.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-extract.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fabs.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fadd.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fcanonicalize.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fceil.mir
|
AMDGPU/GlobalISel: Fix custom legalizatation for fceil
|
2022-01-13 14:29:30 +01:00 |
|
legalize-fcmp.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-fconstant.mir
|
…
|
|
|
legalize-fcopysign.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-fcos.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fdiv.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fexp.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fexp2.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-ffloor.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-flog.mir
|
…
|
|
|
legalize-flog2.mir
|
…
|
|
|
legalize-flog10.mir
|
…
|
|
|
legalize-fma.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fmad.s16.mir
|
…
|
|
|
legalize-fmad.s32.mir
|
…
|
|
|
legalize-fmad.s64.mir
|
…
|
|
|
legalize-fmaxnum.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fminnum.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fmul.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fneg.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fpext.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fpow.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fpowi.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fptosi.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-fptoui.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-fptrunc.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-freeze.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-frint.mir
|
[NFC][AMDGPU][GlobalISel] Fix some legalizer tests
|
2021-11-17 14:25:15 +01:00 |
|
legalize-fshl.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fshr.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-fsin.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fsqrt.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-fsub.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-icmp.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-implicit-def-s1025.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-implicit-def.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-insert-vector-elt.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-insert.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-intrinsic-amdgcn-fdiv-fast.mir
|
…
|
|
|
legalize-intrinsic-round.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-intrinsic-trunc.mir
|
[NFC][AMDGPU][GlobalISel] Fix some legalizer tests
|
2021-11-17 14:25:15 +01:00 |
|
legalize-inttoptr.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-jump-table.mir
|
…
|
|
|
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-llvm.amdgcn.image.dim.a16.ll
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-llvm.amdgcn.image.load.2d.d16.ll
|
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
|
2022-01-10 14:25:14 -05:00 |
|
legalize-llvm.amdgcn.image.load.2d.ll
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.load.3d.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.sample.a16.ll
|
[AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on
|
2021-12-17 16:11:51 +05:30 |
|
legalize-llvm.amdgcn.image.sample.g16.ll
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-llvm.amdgcn.image.store.2d.d16.ll
|
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
|
2022-01-10 14:25:14 -05:00 |
|
legalize-llvm.amdgcn.s.buffer.load.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-load-constant-32bit.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-load-constant.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-load-flat.mir
|
AMDGPU/GlobalISel: Fix assertions on legalize queries with huge align
|
2022-01-12 18:21:44 -05:00 |
|
legalize-load-global.mir
|
[AMDGPU] Remove unused CI check lines
|
2022-01-27 10:53:42 +00:00 |
|
legalize-load-local.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-load-memory-metadata.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-load-private.mir
|
AMDGPU/GlobalISel: Fix test not matching test name
|
2022-01-17 09:38:35 -05:00 |
|
legalize-lshr.mir
|
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
|
2022-01-17 10:04:41 -05:00 |
|
legalize-memcpy.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-memcpyinline.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-memmove.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-memset.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-merge-values-build-vector.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-merge-values.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-mul.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-or.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-phi.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-ptr-add.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-ptrmask.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-ptrtoint.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-rotl-rotr.mir
|
[AMDGPU][GlobalISel] Legalization of G_ROTL and G_ROTR
|
2021-09-07 16:33:24 +02:00 |
|
legalize-sadde.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-saddo.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-saddsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sbfx.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-sdiv.mir
|
[GlobalISel] CSE FP constants at -O0
|
2022-02-10 09:17:11 +00:00 |
|
legalize-select.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sext-inreg.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sext.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sextload-constant-32bit.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-sextload-flat.mir
|
[AMDGPU] Fix some confusing check prefixes. NFC.
|
2022-03-09 17:05:49 +00:00 |
|
legalize-sextload-global.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-sextload-local.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-sextload-private.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-shl.mir
|
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
|
2022-01-17 10:04:41 -05:00 |
|
legalize-shuffle-vector.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-shuffle-vector.s16.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sitofp.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-smax.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-smin.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-smulh.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-smulo.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-srem.mir
|
[GlobalISel] CSE FP constants at -O0
|
2022-02-10 09:17:11 +00:00 |
|
legalize-sshlsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-ssube.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-ssubo.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-ssubsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-store-global.mir
|
[AMDGPU] Update MachineMemOperands syntax in commented out tests
|
2022-01-27 10:56:35 +00:00 |
|
legalize-store.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sub.mir
|
AMDGPU/GlobalISel: Regenerate test checks
|
2021-12-21 10:57:46 -05:00 |
|
legalize-trunc.mir
|
AMDGPU/GlobalISel: Regenerate base test checks
|
2022-01-18 11:26:47 -05:00 |
|
legalize-uadde.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-uaddo.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-uaddsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-ubfx.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-udiv.mir
|
[GlobalISel] CSE FP constants at -O0
|
2022-02-10 09:17:11 +00:00 |
|
legalize-uitofp.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-umax.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-umin.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-umulh.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-umulo.mir
|
[AMDGPU][GlobalISel] Fix legalization of G_UMULH
|
2021-10-05 10:56:02 +01:00 |
|
legalize-unmerge-values.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-urem.mir
|
[GlobalISel] CSE FP constants at -O0
|
2022-02-10 09:17:11 +00:00 |
|
legalize-ushlsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-usube.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-usubo.mir
|
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
|
2021-12-23 14:30:01 +01:00 |
|
legalize-usubsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-vector-args-gfx7.mir
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
legalize-vector-args-gfx8-plus.mir
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
legalize-xor.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-zext.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-zextload-constant-32bit.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-zextload-flat.mir
|
[AMDGPU] Fix some confusing check prefixes. NFC.
|
2022-03-09 17:05:49 +00:00 |
|
legalize-zextload-global.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-zextload-local.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
legalize-zextload-private.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
llvm.abs.ll
|
[AMDGPU][GlobalISel] Legalize G_ABS
|
2021-06-04 14:46:43 +02:00 |
|
llvm.amdgcn.atomic.dec.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.atomic.inc.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.ballot.i32.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.ballot.i64.ll
|
…
|
|
|
llvm.amdgcn.dispatch.id.ll
|
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
|
2022-02-18 16:10:56 +00:00 |
|
llvm.amdgcn.dispatch.ptr.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
llvm.amdgcn.div.fmas.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
llvm.amdgcn.div.scale.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.ds.append.ll
|
…
|
|
|
llvm.amdgcn.ds.consume.ll
|
…
|
|
|
llvm.amdgcn.ds.fadd.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.ds.fmax.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
llvm.amdgcn.ds.fmin.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.ds.gws.barrier.ll
|
…
|
|
|
llvm.amdgcn.ds.gws.init.ll
|
…
|
|
|
llvm.amdgcn.ds.gws.sema.br.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.ds.gws.sema.release.all.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.ds.gws.sema.v.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.ds.ordered.add.gfx10.ll
|
…
|
|
|
llvm.amdgcn.ds.ordered.add.ll
|
…
|
|
|
llvm.amdgcn.ds.ordered.swap.ll
|
…
|
|
|
llvm.amdgcn.end.cf.i32.ll
|
[AMDGPU] Do not generate ELF symbols for the local branch target labels
|
2021-11-20 10:32:41 +05:30 |
|
llvm.amdgcn.end.cf.i64.ll
|
[AMDGPU] Do not generate ELF symbols for the local branch target labels
|
2021-11-20 10:32:41 +05:30 |
|
llvm.amdgcn.fdot2.ll
|
[AMDGPU][GlobalISel] Avoid selecting S_PACK with constants
|
2021-01-20 11:54:53 +01:00 |
|
llvm.amdgcn.fmul.legacy.ll
|
[AMDGPU] Handle legacy multiply-accumulate opcodes in convertToThreeAddress
|
2022-03-01 16:58:00 +00:00 |
|
llvm.amdgcn.global.atomic.csub.ll
|
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
|
2021-06-30 11:45:38 -07:00 |
|
llvm.amdgcn.global.atomic.fadd-with-ret.ll
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
llvm.amdgcn.global.atomic.fadd.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.icmp.ll
|
AMDGPU/GlobalISel: Fix assert on invalid cond code for llvm.amdgcn.icmp
|
2022-01-27 10:34:06 -05:00 |
|
llvm.amdgcn.if.break.i32.ll
|
[AMDGPU] Add volatile support to SIMemoryLegalizer
|
2021-01-09 00:52:33 +00:00 |
|
llvm.amdgcn.if.break.i64.ll
|
[AMDGPU] Add volatile support to SIMemoryLegalizer
|
2021-01-09 00:52:33 +00:00 |
|
llvm.amdgcn.image.atomic.dim.a16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.atomic.dim.ll
|
AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return
|
2021-04-29 20:56:03 +02:00 |
|
llvm.amdgcn.image.atomic.dim.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.image.gather4.a16.dim.ll
|
[AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on
|
2021-12-17 16:11:51 +05:30 |
|
llvm.amdgcn.image.gather4.dim.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.gather4.o.dim.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.getresinfo.a16.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.image.getresinfo.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.image.load.1d.d16.ll
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
llvm.amdgcn.image.load.1d.ll
|
[AMDGPU] Add some image tests with enable-prt-strict-null disabled. NFC.
|
2021-03-31 17:27:20 +01:00 |
|
llvm.amdgcn.image.load.2d.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.load.2darraymsaa.a16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.load.2darraymsaa.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.load.3d.a16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.load.3d.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.sample.g16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.store.2d.d16.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
llvm.amdgcn.image.store.2d.ll
|
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
|
2022-01-10 14:25:14 -05:00 |
|
llvm.amdgcn.implicit.buffer.ptr.ll
|
…
|
|
|
llvm.amdgcn.init.exec.ll
|
…
|
|
|
llvm.amdgcn.init.exec.wave32.ll
|
[AMDGPU] Add some more GFX10 GlobalISel test coverage
|
2021-12-03 13:40:27 +00:00 |
|
llvm.amdgcn.interp.p1.f16.ll
|
…
|
|
|
llvm.amdgcn.intersect_ray.ll
|
[GlobalISel] Fold or of shifts with constant amount to funnel shift.
|
2022-01-24 10:43:32 +05:30 |
|
llvm.amdgcn.is.private.ll
|
AMDGPU: Set up User SGPRs for queue_ptr only when necessary
|
2022-03-09 10:14:05 -08:00 |
|
llvm.amdgcn.is.shared.ll
|
AMDGPU: Set up User SGPRs for queue_ptr only when necessary
|
2022-03-09 10:14:05 -08:00 |
|
llvm.amdgcn.kernarg.segment.ptr.ll
|
AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default
|
2021-12-04 10:38:25 -05:00 |
|
llvm.amdgcn.mfma.gfx90a.ll
|
[AMDGPU] Select VGPR versions of MFMA if possible
|
2022-02-08 10:19:41 -08:00 |
|
llvm.amdgcn.mov.dpp.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.mov.dpp8.ll
|
…
|
|
|
llvm.amdgcn.permlane.ll
|
…
|
|
|
llvm.amdgcn.queue.ptr.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
llvm.amdgcn.raw.buffer.atomic.add.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
|
AMDGPU/GlobalISel: Directly diagnose return value use for FP atomics
|
2022-01-20 12:46:45 -05:00 |
|
llvm.amdgcn.raw.buffer.atomic.fadd.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.load.format.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.load.format.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.store.format.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.store.format.f32.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.buffer.store.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.tbuffer.load.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.tbuffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.tbuffer.store.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.tbuffer.store.i8.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.raw.tbuffer.store.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.rsq.clamp.ll
|
…
|
|
|
llvm.amdgcn.s.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.s.setreg.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.s.sleep.ll
|
…
|
|
|
llvm.amdgcn.sbfe.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
llvm.amdgcn.sdot2.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.sdot4.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.sdot8.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.set.inactive.ll
|
AMDGPU: Don't clobber source register for V_SET_INACTIVE_*
|
2022-02-06 12:38:26 +08:00 |
|
llvm.amdgcn.softwqm.ll
|
…
|
|
|
llvm.amdgcn.struct.buffer.atomic.add.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
|
AMDGPU/GlobalISel: Directly diagnose return value use for FP atomics
|
2022-01-20 12:46:45 -05:00 |
|
llvm.amdgcn.struct.buffer.atomic.fadd.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.load.format.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.load.format.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.store.format.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.store.format.f32.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.buffer.store.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.tbuffer.load.f16.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.struct.tbuffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
llvm.amdgcn.trig.preop.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.ubfe.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
llvm.amdgcn.udot2.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.udot4.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.udot8.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.update.dpp.ll
|
[AMDGPU] Set most sched model resource's BufferSize to one
|
2021-12-01 22:31:28 -08:00 |
|
llvm.amdgcn.workgroup.id.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.workitem.id.ll
|
AMDGPU: Avoid enabling kernel workitem IDs with reqd_work_group_size
|
2022-01-18 13:52:04 -05:00 |
|
llvm.amdgcn.wqm.demote.ll
|
[AMDGPU] Do not generate ELF symbols for the local branch target labels
|
2021-11-20 10:32:41 +05:30 |
|
llvm.amdgcn.wqm.ll
|
…
|
|
|
llvm.amdgcn.wqm.vote.ll
|
…
|
|
|
llvm.amdgcn.writelane.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.wwm.ll
|
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
|
2021-03-03 09:33:57 +01:00 |
|
llvm.memcpy.inline.ll
|
[AMDGPU][GlobalISel] Legalize memcpy family of intrinsics
|
2021-09-07 12:24:07 +02:00 |
|
llvm.memcpy.ll
|
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
|
2021-12-20 18:07:11 -05:00 |
|
llvm.memmove.ll
|
[AMDGPU] Do not generate ELF symbols for the local branch target labels
|
2021-11-20 10:32:41 +05:30 |
|
llvm.memset.ll
|
[AMDGPU] Do not generate ELF symbols for the local branch target labels
|
2021-11-20 10:32:41 +05:30 |
|
llvm.powi.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
llvm.trap.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
load-constant.96.ll
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
load-constant32bit.ll
|
AMDGPU/GlobalISel: Fix selection of constant 32-bit addrspace loads
|
2022-01-17 10:06:33 -05:00 |
|
load-local.96.ll
|
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
|
2021-12-20 18:07:11 -05:00 |
|
load-local.128.ll
|
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
|
2021-12-20 18:07:11 -05:00 |
|
load-unaligned.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
localizer-wrong-insert-point.mir
|
GlobalISel: Fix insert point in localizer
|
2022-01-12 13:44:05 -05:00 |
|
localizer.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
lshr.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
memory-legalizer-atomic-fence.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
merge-buffer-stores.ll
|
[AMDGPU][GlobalISel] Handle G_PTR_ADD when looking for constant offset
|
2021-01-28 11:20:09 +01:00 |
|
minmaxabs.ll
|
…
|
|
|
mubuf-global.ll
|
[AArch64][GlobalISel] Add a new reassociation for G_PTR_ADDs.
|
2021-09-14 23:57:41 -07:00 |
|
mul.ll
|
RegAllocGreedy: Account for reserved registers in num regs heuristic
|
2021-09-14 21:00:29 -04:00 |
|
mul.v2i16.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
no-cse-nonlocal-convergent-instrs.mir
|
[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs
|
2021-05-05 14:22:03 -07:00 |
|
no-legalize-atomic.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
non-entry-alloca.ll
|
AMDGPU: Enable fixed function ABI by default
|
2021-12-04 10:49:18 -05:00 |
|
orn2.ll
|
[AMDGPU] Switch PostRA sched to MachineSched
|
2021-09-14 15:11:27 -04:00 |
|
postlegalizer-combiner-divrem.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizer-combiner-sextload-from-sextinreg.mir
|
AMDGPU: Regenerate some mir test checks with -NEXT
|
2021-12-18 10:46:15 -05:00 |
|
postlegalizer-combiner-unmerge-undef.mir
|
[AMDGPU][GlobalISel] Combine unmerge of undef
|
2022-01-26 12:30:36 +01:00 |
|
postlegalizercombiner-and.mir
|
[GlobalISel] Add a combine for and(load , mask) -> zextload
|
2021-09-16 10:42:46 +02:00 |
|
postlegalizercombiner-load-and-mask.mir
|
[AMDGPU] Regenerate some MIR checks
|
2022-01-20 12:41:40 +00:00 |
|
postlegalizercombiner-sbfx.mir
|
[AMDGPU] Regenerate MIR checks for G_[SU]BFX
|
2022-01-07 12:04:56 +00:00 |
|
postlegalizercombiner-select.mir
|
[AMDGPU][GlobalISel] Combine unmerge of undef
|
2022-01-26 12:30:36 +01:00 |
|
postlegalizercombiner-ubfx.mir
|
[GlobalISel] Use getPreferredShiftAmountTy in one more G_UBFX combine
|
2022-01-08 09:20:44 +00:00 |
|
prelegalizer-combiner-divrem.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
read_register.ll
|
…
|
|
|
readcyclecounter.ll
|
[AMDGPU] Add some GFX10.3 testing. NFC.
|
2021-05-11 11:21:19 +01:00 |
|
regbankcombiner-clamp-fmed3-const.mir
|
AMDGPU/GlobalISel: Add clamp combine
|
2021-12-03 12:49:39 +01:00 |
|
regbankcombiner-clamp-minmax-const.mir
|
AMDGPU/GlobalISel: Add clamp combine
|
2021-12-03 12:49:39 +01:00 |
|
regbankcombiner-fmed3-minmax-const.mir
|
AMDGPU/GlobalISel: Add floating point med3 combine
|
2021-12-03 12:49:39 +01:00 |
|
regbankcombiner-smed3.mir
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
regbankcombiner-umed3.mir
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
regbankselect-add.s16.mir
|
…
|
|
|
regbankselect-add.s32.mir
|
…
|
|
|
regbankselect-add.v2s16.mir
|
…
|
|
|
regbankselect-amdgcn-exp-compr.mir
|
…
|
|
|
regbankselect-amdgcn-exp.mir
|
…
|
|
|
regbankselect-amdgcn-s-buffer-load.mir
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.ballot.i64.mir
|
…
|
|
|
regbankselect-amdgcn.class.mir
|
…
|
|
|
regbankselect-amdgcn.cvt.pkrtz.mir
|
…
|
|
|
regbankselect-amdgcn.div.fmas.mir
|
…
|
|
|
regbankselect-amdgcn.div.scale.mir
|
…
|
|
|
regbankselect-amdgcn.ds.append.mir
|
…
|
|
|
regbankselect-amdgcn.ds.bpermute.mir
|
…
|
|
|
regbankselect-amdgcn.ds.consume.mir
|
…
|
|
|
regbankselect-amdgcn.ds.gws.init.mir
|
…
|
|
|
regbankselect-amdgcn.ds.gws.sema.v.mir
|
…
|
|
|
regbankselect-amdgcn.ds.ordered.add.mir
|
…
|
|
|
regbankselect-amdgcn.ds.ordered.swap.mir
|
…
|
|
|
regbankselect-amdgcn.ds.permute.mir
|
…
|
|
|
regbankselect-amdgcn.ds.swizzle.mir
|
…
|
|
|
regbankselect-amdgcn.else.32.mir
|
…
|
|
|
regbankselect-amdgcn.else.64.mir
|
…
|
|
|
regbankselect-amdgcn.fcmp.mir
|
…
|
|
|
regbankselect-amdgcn.fmul.legacy.mir
|
…
|
|
|
regbankselect-amdgcn.groupstaticsize.mir
|
…
|
|
|
regbankselect-amdgcn.icmp.mir
|
…
|
|
|
regbankselect-amdgcn.image.load.1d.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.image.sample.1d.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.interp.mov.mir
|
…
|
|
|
regbankselect-amdgcn.interp.p1.f16.mir
|
…
|
|
|
regbankselect-amdgcn.interp.p1.mir
|
…
|
|
|
regbankselect-amdgcn.interp.p2.f16.mir
|
…
|
|
|
regbankselect-amdgcn.interp.p2.mir
|
…
|
|
|
regbankselect-amdgcn.kernarg.segment.ptr.mir
|
…
|
|
|
regbankselect-amdgcn.kill.mir
|
…
|
|
|
regbankselect-amdgcn.live.mask.mir
|
[AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic
|
2021-02-15 08:45:46 +09:00 |
|
regbankselect-amdgcn.mfma.gfx90a.mir
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
regbankselect-amdgcn.mfma.mir
|
…
|
|
|
regbankselect-amdgcn.ps.live.mir
|
…
|
|
|
regbankselect-amdgcn.raw.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.readfirstlane.mir
|
…
|
|
|
regbankselect-amdgcn.readlane.mir
|
…
|
|
|
regbankselect-amdgcn.s.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.s.buffer.load.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
|
…
|
|
|
regbankselect-amdgcn.s.getpc.mir
|
…
|
|
|
regbankselect-amdgcn.s.getreg.mir
|
…
|
|
|
regbankselect-amdgcn.s.memrealtime.mir
|
…
|
|
|
regbankselect-amdgcn.s.memtime.mir
|
…
|
|
|
regbankselect-amdgcn.s.sendmsg.mir
|
…
|
|
|
regbankselect-amdgcn.s.sendmsghalt.mir
|
[AMDGPU] Reenable some disabled RUN lines
|
2022-02-15 11:28:24 +00:00 |
|
regbankselect-amdgcn.struct.buffer.load.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.struct.buffer.store.ll
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-amdgcn.update.dpp.mir
|
…
|
|
|
regbankselect-amdgcn.wqm.demote.mir
|
[AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic
|
2021-02-15 08:45:46 +09:00 |
|
regbankselect-amdgcn.wqm.mir
|
…
|
|
|
regbankselect-amdgcn.wqm.vote.mir
|
…
|
|
|
regbankselect-amdgcn.writelane.mir
|
…
|
|
|
regbankselect-amdgcn.wwm.mir
|
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
|
2021-03-03 09:33:57 +01:00 |
|
regbankselect-amdgpu-ffbh-u32.mir
|
[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz
|
2021-08-06 09:40:48 +01:00 |
|
regbankselect-amdgpu-ffbl-b32.mir
|
[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz
|
2021-08-06 09:40:48 +01:00 |
|
regbankselect-amdgpu-wave-address.mir
|
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
|
2022-01-19 10:13:31 -05:00 |
|
regbankselect-and-s1.mir
|
…
|
|
|
regbankselect-and.mir
|
…
|
|
|
regbankselect-anyext.mir
|
…
|
|
|
regbankselect-ashr.mir
|
[AMDGPU][GlobalISel] Fix v2s16 right shifts
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-assert-align.mir
|
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
|
2022-01-24 09:26:52 -05:00 |
|
regbankselect-atomic-cmpxchg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-add.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-and.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-fadd.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-max.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-min.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-or.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-sub.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-umax.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-umin.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-xchg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-atomicrmw-xor.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-bitcast.mir
|
…
|
|
|
regbankselect-bitreverse.mir
|
[AMDGPU] Better codegen for i64 bitreverse
|
2021-02-26 15:51:36 +00:00 |
|
regbankselect-block-addr.mir
|
…
|
|
|
regbankselect-brcond.mir
|
…
|
|
|
regbankselect-bswap.mir
|
…
|
|
|
regbankselect-build-vector-trunc.mir
|
…
|
|
|
regbankselect-build-vector-trunc.v2s16.mir
|
…
|
|
|
regbankselect-build-vector.mir
|
…
|
|
|
regbankselect-concat-vector.mir
|
…
|
|
|
regbankselect-constant.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-copy.mir
|
…
|
|
|
regbankselect-ctlz-zero-undef.mir
|
[AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR ctlz_zero_undef/cttz_zero_undef
|
2021-08-06 09:40:48 +01:00 |
|
regbankselect-ctpop.mir
|
…
|
|
|
regbankselect-cttz-zero-undef.mir
|
[AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32
|
2021-08-17 18:09:57 +01:00 |
|
regbankselect-default.mir
|
…
|
|
|
regbankselect-dyn-stackalloc.mir
|
[AMDGPU] Reenable some disabled RUN lines
|
2022-02-15 11:28:24 +00:00 |
|
regbankselect-extract-vector-elt.mir
|
[AMDGPU] Reenable some disabled RUN lines
|
2022-02-15 11:28:24 +00:00 |
|
regbankselect-extract.mir
|
…
|
|
|
regbankselect-fabs.mir
|
…
|
|
|
regbankselect-fadd.mir
|
…
|
|
|
regbankselect-fcanonicalize.mir
|
…
|
|
|
regbankselect-fceil.mir
|
…
|
|
|
regbankselect-fcmp.mir
|
…
|
|
|
regbankselect-fexp2.mir
|
…
|
|
|
regbankselect-flog2.mir
|
…
|
|
|
regbankselect-fma.mir
|
…
|
|
|
regbankselect-fmul.mir
|
…
|
|
|
regbankselect-fneg.mir
|
…
|
|
|
regbankselect-fpext.mir
|
…
|
|
|
regbankselect-fptosi.mir
|
…
|
|
|
regbankselect-fptoui.mir
|
…
|
|
|
regbankselect-fptrunc.mir
|
…
|
|
|
regbankselect-frame-index.mir
|
…
|
|
|
regbankselect-freeze.mir
|
…
|
|
|
regbankselect-frint.mir
|
…
|
|
|
regbankselect-fshr.mir
|
…
|
|
|
regbankselect-fsqrt.mir
|
…
|
|
|
regbankselect-fsub.mir
|
…
|
|
|
regbankselect-icmp.mir
|
…
|
|
|
regbankselect-icmp.s16.mir
|
…
|
|
|
regbankselect-illegal-copy.mir
|
…
|
|
|
regbankselect-insert-vector-elt.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-insert.mir
|
…
|
|
|
regbankselect-intrinsic-trunc.mir
|
…
|
|
|
regbankselect-inttoptr.mir
|
…
|
|
|
regbankselect-load.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
regbankselect-lshr.mir
|
[AMDGPU][GlobalISel] Fix v2s16 right shifts
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-merge-values.mir
|
…
|
|
|
regbankselect-mul.mir
|
…
|
|
|
regbankselect-or.mir
|
…
|
|
|
regbankselect-phi-s1.mir
|
…
|
|
|
regbankselect-phi.mir
|
…
|
|
|
regbankselect-ptr-add.mir
|
…
|
|
|
regbankselect-ptrmask.mir
|
…
|
|
|
regbankselect-ptrtoint.mir
|
…
|
|
|
regbankselect-reg-sequence.mir
|
…
|
|
|
regbankselect-sadde.mir
|
…
|
|
|
regbankselect-sbfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
regbankselect-select.mir
|
…
|
|
|
regbankselect-sext-inreg.mir
|
…
|
|
|
regbankselect-sext.mir
|
…
|
|
|
regbankselect-sextload.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-shl.mir
|
…
|
|
|
regbankselect-shuffle-vector.mir
|
…
|
|
|
regbankselect-sitofp.mir
|
…
|
|
|
regbankselect-smax.mir
|
[AMDGPU][GlobalISel] Use scalar min/max instructions
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-smin.mir
|
[AMDGPU][GlobalISel] Use scalar min/max instructions
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-smulh.mir
|
…
|
|
|
regbankselect-split-scalar-load-metadata.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
regbankselect-ssube.mir
|
…
|
|
|
regbankselect-sub.mir
|
…
|
|
|
regbankselect-trunc.mir
|
…
|
|
|
regbankselect-uadde.mir
|
…
|
|
|
regbankselect-uaddo.mir
|
…
|
|
|
regbankselect-ubfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
regbankselect-uitofp.mir
|
…
|
|
|
regbankselect-umax.mir
|
[AMDGPU][GlobalISel] Use scalar min/max instructions
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-umin.mir
|
[AMDGPU][GlobalISel] Use scalar min/max instructions
|
2021-02-04 17:04:32 +00:00 |
|
regbankselect-umulh.mir
|
[AMDGPU] Reenable some disabled RUN lines
|
2022-02-15 11:28:24 +00:00 |
|
regbankselect-uniform-load-noclobber.mir
|
GlobalISel: Preserve memory type when reducing load/store width
|
2021-06-30 17:05:29 -04:00 |
|
regbankselect-unmerge-values.mir
|
…
|
|
|
regbankselect-usube.mir
|
…
|
|
|
regbankselect-usubo.mir
|
…
|
|
|
regbankselect-waterfall-agpr.mir
|
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
|
2022-01-12 13:44:05 -05:00 |
|
regbankselect-widen-scalar-loads.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-xor.mir
|
…
|
|
|
regbankselect-zext.mir
|
…
|
|
|
regbankselect-zextload.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
ret.ll
|
…
|
|
|
roundeven.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
saddsat.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
sbfx.ll
|
[AMDGPU] Regenerate G_[SU]BFX checks using some common prefixes
|
2022-01-07 12:04:56 +00:00 |
|
sdiv.i32.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
sdiv.i64.ll
|
[StructurizeCFG] Clean up some boolean not instructions
|
2022-02-01 09:35:37 +00:00 |
|
sdivrem.ll
|
[LSV] Vectorize loads of vectors by turning it into a larger vector
|
2022-01-26 11:38:41 +01:00 |
|
shader-epilogs.ll
|
…
|
|
|
shl-ext-reduce.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
shl.ll
|
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
|
2022-01-17 10:04:41 -05:00 |
|
shlN_add.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
smed3.ll
|
AMDGPU/GlobalISel: Fix constant bus restriction errors for med3
|
2021-12-01 21:36:37 +01:00 |
|
smrd.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
srem.i32.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
srem.i64.ll
|
[StructurizeCFG] Clean up some boolean not instructions
|
2022-02-01 09:35:37 +00:00 |
|
ssubsat.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
store-local.96.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
store-local.128.ll
|
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
|
2022-01-20 12:12:05 -05:00 |
|
trunc.ll
|
…
|
|
|
uaddsat.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
ubfx.ll
|
[GlobalISel] Use getPreferredShiftAmountTy in one more G_UBFX combine
|
2022-01-08 09:20:44 +00:00 |
|
udiv.i32.ll
|
[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
|
2021-10-07 23:51:37 -07:00 |
|
udiv.i64.ll
|
[StructurizeCFG] Clean up some boolean not instructions
|
2022-02-01 09:35:37 +00:00 |
|
udivrem.ll
|
[LSV] Vectorize loads of vectors by turning it into a larger vector
|
2022-01-26 11:38:41 +01:00 |
|
umed3.ll
|
AMDGPU/GlobalISel: Fix constant bus restriction errors for med3
|
2021-12-01 21:36:37 +01:00 |
|
urem.i32.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
urem.i64.ll
|
[AMDGPU] Make more use of madmk/fmamk instructions
|
2022-03-02 10:22:10 +00:00 |
|
usubsat.ll
|
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
|
2022-03-09 12:18:02 +05:30 |
|
widen-i8-i16-scalar-loads.ll
|
[AMDGPU] Set MemoryVT for truncstores in tblgen.
|
2022-01-20 19:05:12 +05:30 |
|
write_register.ll
|
…
|
|
|
xnor.ll
|
[GlobalISel][Legalizer] Use ArtifactValueFinder first for unmerge combines before trying others.
|
2021-09-21 00:02:15 -07:00 |
|
zextload.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
