..
32abi.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
64abi.ll
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
2018-05-01 19:26:15 +00:00
64bit.ll
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64cond.ll
[Sparc] Return true in enableMultipleCopyHints().
2018-02-24 08:24:31 +00:00
64spill.ll
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2006-01-22-BitConvertLegalize.ll
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2007-05-09-JumpTables.ll
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2007-07-05-LiveIntervalAssert.ll
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2008-10-10-InlineAsmMemoryOperand.ll
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2008-10-10-InlineAsmRegOperand.ll
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2009-08-28-PIC.ll
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2009-08-28-WeakLinkage.ll
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2011-01-11-CC.ll
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2011-01-11-Call.ll
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2011-01-11-FrameAddr.ll
[Sparc] Flush register windows for @llvm.returnaddress(1)
2018-08-17 09:18:31 +00:00
2011-01-19-DelaySlot.ll
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2011-01-21-ByValArgs.ll
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2011-01-22-SRet.ll
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2011-12-03-TailDuplication.ll
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2012-05-01-LowerArguments.ll
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2013-05-17-CallFrame.ll
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DbgValueOtherTargets.test
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LeonCASAInstructionUT.ll
Add support for Myriad ma2x8x series of CPUs
2017-10-02 18:50:48 +00:00
LeonDetectRoundChangePassUT.ll
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LeonFixAllFDIVSQRTPassUT.ll
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LeonInsertNOPLoadPassUT.ll
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LeonItinerariesUT.ll
[CodeGen] Always use `printReg` to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
LeonSMACUMACInstructionUT.ll
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analyze-branch.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
atomics.ll
[Sparc] Use synthetic instruction clr to zero register instead of sethi
2018-04-20 07:47:12 +00:00
basictest.ll
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blockaddr.ll
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cast-sret-func.ll
[Sparc] Get sret arg size from CallLoweringInfo.getArgs()
2018-08-17 10:40:00 +00:00
constpool.ll
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constructor.ll
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ctpop.ll
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disable-fsmuld-fmuls.ll
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empty-functions.ll
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exception.ll
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fail-alloca-align.ll
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float-constants.ll
[Sparc] Custom bitcast between f64 and v2i32
2018-08-27 07:14:53 +00:00
float.ll
Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion
2017-12-11 22:25:04 +00:00
fp128.ll
[Sparc] Get sret arg size from CallLoweringInfo.getArgs()
2018-08-17 10:40:00 +00:00
func-addr.ll
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globals.ll
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imm.ll
[Sparc] Use synthetic instruction clr to zero register instead of sethi
2018-04-20 07:47:12 +00:00
inlineasm-bad.ll
[Sparc] Select correct register class for FP register constraints
2018-05-30 06:07:55 +00:00
inlineasm-v9.ll
[Sparc] Select correct register class for FP register constraints
2018-05-30 06:07:55 +00:00
inlineasm.ll
Revert "[Sparc] Use the IntPair reg class for r constraints with value type f64"
2018-07-18 10:05:30 +00:00
leafproc.ll
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lit.local.cfg
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mature-mc-support.ll
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missing-sret.ll
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missinglabel.ll
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mult-alt-generic-sparc.ll
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multiple-div.ll
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obj-relocs.ll
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parts.ll
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pic.ll
[Sparc] Add support for 13-bit PIC
2018-06-11 05:50:08 +00:00
private.ll
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readcycle.ll
[Sparc] Add support for the cycle counter available in GR740
2018-08-27 11:11:47 +00:00
register-clobber.ll
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rem.ll
Regenerate remainder test.
2018-07-20 13:14:29 +00:00
reserved-regs.ll
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select-mask.ll
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setjmp.ll
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sjlj.ll
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soft-float.ll
NFC - Various typo fixes in tests
2018-07-04 13:28:39 +00:00
soft-mul-div.ll
[Sparc] Use the names .rem and .urem instead of __modsi3 and __umodsi3
2018-07-16 12:22:08 +00:00
spill.ll
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spillsize.ll
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sret-secondary.ll
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stack-align.ll
[Sparc] Account for bias in stack readjustment
2018-01-29 12:10:32 +00:00
stack-protector.ll
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thread-pointer.ll
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tls.ll
[Sparc] Include __tls_get_addr in symbol table for TLS calls to it
2018-02-21 15:25:26 +00:00
trap.ll
[Sparc] Do not depend on icc for ta 1
2018-07-17 05:49:33 +00:00
umulo-128-legalisation-lowering.ll
[SelectionDAG] Improve the legalisation lowering of UMULO.
2018-08-16 18:39:39 +00:00
varargs-v8.ll
Avoid losing Hi part when expanding VAARG nodes on big endian machines
2018-07-16 12:14:17 +00:00
varargs.ll
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vector-call.ll
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vector-extract-elt.ll
[Sparc] Use synthetic instruction clr to zero register instead of sethi
2018-04-20 07:47:12 +00:00
zerostructcall.ll
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