llvm-project/llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll

98 lines
3.0 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: addw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bge a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a3, a2, a3
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: srli a2, a2, 32
; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: mul a1, a2, a1
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: add a0, a3, a0
; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: ret
entry:
%cmp6 = icmp slt i32 %s, %n
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = xor i32 %s, -1
%1 = add i32 %0, %n
%2 = add i32 %s, 1
%3 = mul i32 %1, %2
%4 = zext i32 %1 to i33
%5 = add i32 %n, -2
%6 = sub i32 %5, %s
%7 = zext i32 %6 to i33
%8 = mul i33 %4, %7
%9 = lshr i33 %8, 1
%10 = trunc i33 %9 to i32
%11 = add i32 %3, %s
%12 = add i32 %11, %10
br label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.body.preheader, %entry
%sum.0.lcssa = phi i32 [ 0, %entry ], [ %12, %for.body.preheader ]
ret i32 %sum.0.lcssa
}
define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: subw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bge a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: mul a2, a3, a2
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: srli a3, a3, 32
; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: mul a1, a3, a1
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: sub a0, a2, a0
; CHECK-NEXT: subw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: ret
entry:
%cmp6 = icmp slt i32 %s, %n
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = xor i32 %s, -1
%1 = add i32 %0, %n
%2 = xor i32 %s, -1
%3 = mul i32 %1, %2
%4 = zext i32 %1 to i33
%5 = add i32 %n, -2
%6 = sub i32 %5, %s
%7 = zext i32 %6 to i33
%8 = mul i33 %4, %7
%9 = lshr i33 %8, 1
%10 = trunc i33 %9 to i32
%11 = sub i32 %3, %s
%12 = sub i32 %11, %10
br label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.body.preheader, %entry
%sum.0.lcssa = phi i32 [ 0, %entry ], [ %12, %for.body.preheader ]
ret i32 %sum.0.lcssa
}