forked from OSchip/llvm-project
36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IF %s
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define zeroext i1 @float_is_nan(float %a) nounwind {
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; RV32IF-LABEL: float_is_nan:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: feq.s a0, fa0, fa0
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; RV32IF-NEXT: seqz a0, a0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: float_is_nan:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: feq.s a0, fa0, fa0
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; RV64IF-NEXT: seqz a0, a0
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; RV64IF-NEXT: ret
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%1 = fcmp uno float %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @float_not_nan(float %a) nounwind {
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; RV32IF-LABEL: float_not_nan:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: feq.s a0, fa0, fa0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: float_not_nan:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: feq.s a0, fa0, fa0
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; RV64IF-NEXT: ret
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%1 = fcmp ord float %a, 0.000000e+00
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ret i1 %1
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}
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